diff --git a/src/acpi/fadt/fadt.c b/src/acpi/fadt/fadt.c
index cbe8f05..90f5d54 100644
--- a/src/acpi/fadt/fadt.c
+++ b/src/acpi/fadt/fadt.c
@@ -72,6 +72,88 @@ static int fadt_init(fwts_framework *fw)
 	return FWTS_OK;
 }
 
+static void flag_info(fwts_framework *fw, const char *name, int state)
+{
+	const char *enabled = "set";
+	const char *disabled = "not set";
+	const char *ptr;
+
+	ptr = (state) ? enabled : disabled;
+	fwts_log_info(fw, "     %s is %s", name, ptr);
+}
+
+static int fadt_info(fwts_framework *fw)
+{
+	fwts_log_info(fw, "FADT: flag states");
+	flag_info(fw, "WBINVD",
+		  fadt->flags & FWTS_FACP_FLAG_WBINVD);
+	flag_info(fw, "WBINVD_FLUSH",
+		  fadt->flags & FWTS_FACP_FLAG_WBINVD_FLUSH);
+	flag_info(fw, "PROC_C1",
+		  fadt->flags & FWTS_FACP_FLAG_PROC_C1);
+	flag_info(fw, "P_LVL2_UP",
+		  fadt->flags & FWTS_FACP_FLAG_P_LVL2_UP);
+	flag_info(fw, "PWR_BUTTON",
+		  fadt->flags & FWTS_FACP_FLAG_PWR_BUTTON);
+	flag_info(fw, "SLP_BUTTON",
+		  fadt->flags & FWTS_FACP_FLAG_SLP_BUTTON);
+	flag_info(fw, "FIX_RTC",
+		  fadt->flags & FWTS_FACP_FLAG_FIX_RTC);
+	flag_info(fw, "RTC_S4",
+		  fadt->flags & FWTS_FACP_FLAG_RTC_S4);
+	flag_info(fw, "TMR_VAL_EXT",
+		  fadt->flags & FWTS_FACP_FLAG_TMR_VAL_EXT);
+	flag_info(fw, "DCK_CAP",
+		  fadt->flags & FWTS_FACP_FLAG_DCK_CAP);
+	flag_info(fw, "RESET_REG_SUP",
+		  fadt->flags & FWTS_FACP_FLAG_RESET_REG_SUP);
+	flag_info(fw, "SEALED_CASE",
+		  fadt->flags & FWTS_FACP_FLAG_SEALED_CASE);
+	flag_info(fw, "HEADLESS",
+		  fadt->flags & FWTS_FACP_FLAG_HEADLESS);
+	flag_info(fw, "CPU_SW_SLP",
+		  fadt->flags & FWTS_FACP_FLAG_CPU_SW_SLP);
+	flag_info(fw, "PCI_EXP_WAK",
+		  fadt->flags & FWTS_FACP_FLAG_PCI_EXP_WAK);
+	flag_info(fw, "USE_PLATFORM_CLOCK",
+		  fadt->flags & FWTS_FACP_FLAG_USE_PLATFORM_CLOCK);
+	flag_info(fw, "S4_RTC_STS_VALID",
+		  fadt->flags & FWTS_FACP_FLAG_S4_RTC_STS_VALID);
+	flag_info(fw, "REMOTE_POWER_ON_CAPABLE",
+		  fadt->flags & FWTS_FACP_FLAG_REMOTE_POWER_ON_CAPABLE);
+	flag_info(fw, "FORCE_APIC_CLUSTER_MODEL",
+		  fadt->flags & FWTS_FACP_FLAG_FORCE_APIC_CLUSTER_MODEL);
+	flag_info(fw, "FORCE_APIC_PHYSICAL_DESTINATION_MODE",
+		  fadt->flags & FWTS_FACP_FLAG_FORCE_APIC_PHYSICAL_DESTINATION_MODE);
+	flag_info(fw, "HW_REDUCED_ACPI",
+		  fadt->flags & FWTS_FACP_FLAG_HW_REDUCED_ACPI);
+	flag_info(fw, "LOW_POWER_S0_IDLE_CAPABLE",
+		  fadt->flags & FWTS_FACP_FLAG_LOW_POWER_S0_IDLE_CAPABLE);
+
+	fwts_log_info(fw, "FADT: IA-PC Boot Architecture flag states");
+	flag_info(fw, "LEGACY_DEVICES", fadt->iapc_boot_arch &
+		  FWTS_FACP_IAPC_BOOT_ARCH_LEGACY_DEVICES);
+	flag_info(fw, "8042", fadt->iapc_boot_arch &
+		  FWTS_FACP_IAPC_BOOT_ARCH_8042);
+	flag_info(fw, "VGA_NOT_PRESENT", fadt->iapc_boot_arch &
+		  FWTS_FACP_IAPC_BOOT_ARCH_VGA_NOT_PRESENT);
+	flag_info(fw, "MSI_NOT_SUPPORTED", fadt->iapc_boot_arch &
+		  FWTS_FACP_IAPC_BOOT_ARCH_MSI_NOT_SUPPORTED);
+	flag_info(fw, "PCIE_ASPM_CONTROLS", fadt->iapc_boot_arch &
+		  FWTS_FACP_IAPC_BOOT_ARCH_PCIE_ASPM_CONTROLS);
+	flag_info(fw, "CMOS_RTC_NOT_PRESENT", fadt->iapc_boot_arch &
+		  FWTS_FACP_IAPC_BOOT_ARCH_CMOS_RTC_NOT_PRESENT);
+
+	fwts_log_info(fw, "FADT: ARM Boot Architecture flag states");
+	flag_info(fw, "PSCI_COMPLIANT", fadt->arm_boot_flags &
+		  FWTS_FACP_ARM_BOOT_ARCH_PSCI_COMPLIANT);
+	flag_info(fw, "PSCI_USE_HVC", fadt->arm_boot_flags &
+		  FWTS_FACP_ARM_BOOT_ARCH_PSCI_USE_HVC);
+
+	fwts_infoonly(fw);
+	return FWTS_OK;
+}
+
 static void acpi_table_check_fadt_firmware_control(
 	fwts_framework *fw,
 	const fwts_acpi_table_fadt *fadt,
@@ -559,6 +641,7 @@ static int fadt_test3(fwts_framework *fw)
 }
 
 static fwts_framework_minor_test fadt_tests[] = {
+	{ fadt_info, "FADT ACPI Description Table flag info." },
 	{ fadt_test1, "Test FADT ACPI Description Table tests." },
 	{ fadt_test2, "Test FADT SCI_EN bit is enabled." },
 	{ fadt_test3, "Test FADT reset register." },
diff --git a/src/lib/include/fwts_acpi.h b/src/lib/include/fwts_acpi.h
index a8a8276..8f80286 100644
--- a/src/lib/include/fwts_acpi.h
+++ b/src/lib/include/fwts_acpi.h
@@ -32,11 +32,41 @@
 #define FWTS_FACP_PERFORMANCE_SERVER		(0x07)
 #define FWTS_FACP_TABLET			(0x08)
 
+#define FWTS_FACP_FLAG_WBINVD					(0x00000001)
+#define FWTS_FACP_FLAG_WBINVD_FLUSH				(0x00000002)
+#define FWTS_FACP_FLAG_PROC_C1					(0x00000004)
+#define FWTS_FACP_FLAG_P_LVL2_UP				(0x00000008)
+#define FWTS_FACP_FLAG_PWR_BUTTON				(0x00000010)
+#define FWTS_FACP_FLAG_SLP_BUTTON				(0x00000020)
+#define FWTS_FACP_FLAG_FIX_RTC					(0x00000040)
+#define FWTS_FACP_FLAG_RTC_S4					(0x00000080)
+#define FWTS_FACP_FLAG_TMR_VAL_EXT				(0x00000100)
+#define FWTS_FACP_FLAG_DCK_CAP					(0x00000200)
+#define FWTS_FACP_FLAG_RESET_REG_SUP				(0x00000400)
+#define FWTS_FACP_FLAG_SEALED_CASE				(0x00000800)
+#define FWTS_FACP_FLAG_HEADLESS					(0x00001000)
+#define FWTS_FACP_FLAG_CPU_SW_SLP				(0x00002000)
+#define FWTS_FACP_FLAG_PCI_EXP_WAK				(0x00004000)
+#define FWTS_FACP_FLAG_USE_PLATFORM_CLOCK			(0x00008000)
+#define FWTS_FACP_FLAG_S4_RTC_STS_VALID				(0x00010000)
+#define FWTS_FACP_FLAG_REMOTE_POWER_ON_CAPABLE			(0x00020000)
+#define FWTS_FACP_FLAG_FORCE_APIC_CLUSTER_MODEL			(0x00040000)
+#define FWTS_FACP_FLAG_FORCE_APIC_PHYSICAL_DESTINATION_MODE	(0x00080000)
+#define FWTS_FACP_FLAG_HW_REDUCED_ACPI				(0x00100000)
+#define FWTS_FACP_FLAG_LOW_POWER_S0_IDLE_CAPABLE		(0x00200000)
+#define FWTS_FACP_FLAG_RESERVED_MASK				(0xffc00000)
+
 #define FWTS_FACP_IAPC_BOOT_ARCH_LEGACY_DEVICES		(0x0001)
 #define FWTS_FACP_IAPC_BOOT_ARCH_8042			(0x0002)
 #define FWTS_FACP_IAPC_BOOT_ARCH_VGA_NOT_PRESENT	(0x0004)
 #define FWTS_FACP_IAPC_BOOT_ARCH_MSI_NOT_SUPPORTED	(0x0008)
 #define FWTS_FACP_IAPC_BOOT_ARCH_PCIE_ASPM_CONTROLS	(0x0010)
+#define FWTS_FACP_IAPC_BOOT_ARCH_CMOS_RTC_NOT_PRESENT	(0x0020)
+#define FWTS_FACP_IAPC_BOOT_ARCH_RESERVED_MASK		(0xffc0)
+
+#define FWTS_FACP_ARM_BOOT_ARCH_PSCI_COMPLIANT		(0x0001)
+#define FWTS_FACP_ARM_BOOT_ARCH_PSCI_USE_HVC		(0x0002)
+#define FWTS_FACP_ARM_BOOT_ARCH_RESERVED_MASK		(0xfffc)
 
 #define FWTS_GAS_ADDR_SPACE_ID_SYSTEM_MEMORY	(0x00)
 #define FWTS_GAS_ADDR_SPACE_ID_SYSTEM_IO	(0x01)
