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[192.237.175.120]) by mx.google.com with ESMTPS id p54si11554209qta.8.2016.05.23.07.19.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 May 2016 07:19:22 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qgK-0003s7-7v; Mon, 23 May 2016 14:18:08 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qgI-0003pr-VF for xen-devel@lists.xen.org; Mon, 23 May 2016 14:18:07 +0000 Received: from [85.158.139.211] by server-11.bemta-5.messagelabs.com id 3B/05-02219-E1113475; Mon, 23 May 2016 14:18:06 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTVdW0Dn c4OFZHYslHxezODB6HN39mymAMYo1My8pvyKBNeP0942sBSulK66t/svWwPhHuIuRi0NIYCOj xNT37YwQzmlGie9fprF1MXJysAloStz5/IkJxBYRkJa49vkyWBGzwBxGiTUP/jKDJIQFfCR2H 9wEVMTBwSKgKtG1KB8kzCvgKrH+1V1GEFtCQE7i5LHJrCA2J1B8+5dzYHEhAReJjls72Scwci 9gZFjFqFGcWlSWWqRraKqXVJSZnlGSm5iZo2toYKqXm1pcnJiempOYVKyXnJ+7iRHoYQYg2MH YsN3zEKMkB5OSKO/JHU7hQnxJ+SmVGYnFGfFFpTmpxYcYZTg4lCR4N/M7hwsJFqWmp1akZeYA Qw0mLcHBoyTCe4gPKM1bXJCYW5yZDpE6xagoJc47DaRPACSRUZoH1wYL70uMslLCvIxAhwjxF KQW5WaWoMq/YhTnYFQS5t0CMoUnM68EbvoroMVMQIsfSjuALC5JREhJNTCyGymr7lsY18Yula 72pmTu9Xzp0tvtzAF8KZNyjP8pxj7Pbeore/jxe4Pirnj/Vf9PqM0sn3WysWWZO/eDvaxX59l sNf7170ZiLvde7m8ONsJ3ec56b4sxCZgov9B9Tr77onMcoUmK343ZM1UZ/rUdCzjBxxhV1HGm v/d33ZTHytIfXbI+6imxFGckGmoxFxUnAgCYK5G2agIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-3.tower-206.messagelabs.com!1464013068!37465424!12 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36563 invoked from network); 23 May 2016 14:18:05 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-206.messagelabs.com with SMTP; 23 May 2016 14:18:05 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2873959; Mon, 23 May 2016 07:18:27 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA4DD3F21A; Mon, 23 May 2016 07:18:03 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 23 May 2016 15:17:32 +0100 Message-Id: <1464013052-32587-16-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464013052-32587-1-git-send-email-julien.grall@arm.com> References: <1464013052-32587-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, wei.liu2@citrix.com, steve.capper@arm.com, andre.przywara@arm.com, Julien Grall , wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2 15/15] xen/arm: arm64: Document Cortex-A57 erratum 834220 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The ARM erratum applies to certain revisions of Cortex-A57. The processor may report a Stage 2 translation fault as the result of Stage 1 fault for load crossing a page boundary when there is a permission fault or device memory fault at stage 1 and a translation fault at Stage 2. So Xen needs to check that Stage 1 translation does not generate a fault before handling the Stage 2 fault. If it is a Stage 1 translation fault, return to the guest to let the processor injecting the correct fault. Only document it as this is already the behavior of the fault handlers. Note that some optimization could be done to avoid unecessary translation fault. This is because HPFAR_EL2 is valid for more use case. For the moment, the code is left unmodified. Signed-off-by: Julien Grall --- docs/misc/arm/silicon-errata.txt | 1 + xen/arch/arm/traps.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index ab2e5bc..1ac365d 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -47,3 +47,4 @@ stable hypervisors. | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +| ARM | Cortex-A57 | #834220 | N/A | diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 3acdba0..bbd5309 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2396,6 +2396,21 @@ static void do_trap_instr_abort_guest(struct cpu_user_regs *regs, .kind = hsr.iabt.s1ptw ? npfec_kind_in_gpt : npfec_kind_with_gla }; + /* + * Erratum #834220: The processor may report a Stage 2 + * translation fault as the result of Stage 1 fault for load + * crossing a page boundary when there is a permission fault or + * device memory alignment fault at Stage 1 and a translation + * fault at Stage 2. + * + * So Xen needs to check that the Stage 1 translation does not + * generate a fault before handling stage 2 fault. If it is a Stage + * 1 translation fault, return to the guest to let the processor + * injecting the correct fault. + * + * XXX: This can be optimized to avoid some unecessary + * translation. + */ if ( hsr.iabt.s1ptw ) gpa = get_faulting_ipa(); else @@ -2445,6 +2460,21 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, info.gva = READ_SYSREG64(FAR_EL2); #endif + /* + * Erratum #834220: The processor may report a Stage 2 + * translation fault as the result of Stage 1 fault for load + * crossing a page boundary when there is a permission fault or + * device memory alignment fault at Stage 1 and a translation + * fault at Stage 2. + * + * So Xen needs to check that the Stage 1 translation does not + * generate a fault before handling stage 2 fault. If it is a Stage + * 1 translation fault, return to the guest to let the processor + * injecting the correct fault. + * + * XXX: This can be optimized to avoid some unecessary + * translation. + */ if ( dabt.s1ptw ) info.gpa = get_faulting_ipa(); else