From patchwork Mon Dec 5 17:43:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 86599 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1607559qgi; Mon, 5 Dec 2016 09:46:34 -0800 (PST) X-Received: by 10.107.138.142 with SMTP id c14mr25235621ioj.213.1480959994406; Mon, 05 Dec 2016 09:46:34 -0800 (PST) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id m69si645731itm.53.2016.12.05.09.46.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Dec 2016 09:46:34 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cDxIb-0007Iy-Ai; Mon, 05 Dec 2016 17:43:33 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cDxIa-0007Ir-1t for xen-devel@lists.xen.org; Mon, 05 Dec 2016 17:43:32 +0000 Received: from [85.158.143.35] by server-5.bemta-6.messagelabs.com id DA/E4-19272-347A5485; Mon, 05 Dec 2016 17:43:31 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLLMWRWlGSWpSXmKPExsVysyfVTdd5uWu EwbYHLBZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8afPyeYCx6JVFw/OputgfGXQBcjF4eQwCZG iVsNa1khnNOMEvsu72fuYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWcBB4s3HeyxdjBwcwgJ2E m9nWYGEWQRUJeZe2AxWwivgLNF56zfYGAkBOYmTxyazTmDkXMDIsIpRvTi1qCy1SNdML6koMz 2jJDcxM0fX0MBMLze1uDgxPTUnMalYLzk/dxMj0FsMQLCDcd4J/0OMkhxMSqK8UxJcI4T4kvJ TKjMSizPii0pzUosPMcpwcChJ8L5ZCpQTLEpNT61Iy8wBhg1MWoKDR0mEdzdImre4IDG3ODMd InWKUVFKnPceSEIAJJFRmgfXBgvVS4yyUsK8jECHCPEUpBblZpagyr9iFOdgVBLmrVsGNIUnM 68EbvoroMVMQItPHHcGWVySiJCSamAU4b3ZcODw44eTNc3E58/4aCBf9PX8uSkKpXPOJNhaav BcF5nifqnkar+qWOTHWuPNv4KFJl5asrRfK+ipkdyDN0YfAmae899iILvt1sT8RA3zpwa8iY8 OMc5baTBFJ3PjEv1I/2OTHLLtpsqKCxyanfJjrkHY383/nr2p8JvNLWt9P+XD3qjPSizFGYmG WsxFxYkAl2fiFlACAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-8.tower-21.messagelabs.com!1480959810!46641439!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 33568 invoked from network); 5 Dec 2016 17:43:30 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-8.tower-21.messagelabs.com with SMTP; 5 Dec 2016 17:43:30 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 006D6707; Mon, 5 Dec 2016 09:43:30 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 621833F483; Mon, 5 Dec 2016 09:43:29 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Dec 2016 17:43:23 +0000 Message-Id: <1480959803-4206-1-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 Cc: Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH] xen/arm: traps: Emulate ICC_SRE_EL1 as RAZ/WI X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Recent Linux kernel (4.4 and onwards [1]) is checking whether it is possible to enable sysreg access (ICC_SRE_EL1.SRE) when the ID register (ID_AA64PRF0_EL1.GIC) is reporting the presence of the sysreg interface. When the guest has been configured to use GICv2, the hypervisor will disable sysreg access for this vm (via ICC_SRE_EL2.Enable) and therefore access to system register such as ICC_SRE_EL1 are trapped in EL2. However, ICC_SRE_EL1 is not emulated by the hypervisor. This means that Linux will crash as soon as it is trying to access ICC_SRE_EL1. To solve this problem, Xen can implement ICC_SRE_EL1 as read-as-zero write-ignore. The emulation will only be used when sysreg are disabled for EL1. [1] 963fcd409 "arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF" Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- I think this patch would need to be backported as recent Linux (4.4 and onwards) are trying to access ICC_EL1_SRE during boot time. The first support of GICv2 on GICv3 was in Xen 4.6. --- xen/arch/arm/traps.c | 14 ++++++++++++++ xen/include/asm-arm/sysregs.h | 1 + 2 files changed, 15 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 8ff73fe..ae921d7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2280,6 +2280,20 @@ static void do_sysreg(struct cpu_user_regs *regs, return inject_undef64_exception(regs, hsr.len); /* + * ICC_SRE_EL2.Enable = 0 + * + * GIC Architecture Specification (IHI 0069C): Section 8.1.9 + */ + case HSR_SYSREG_ICC_SRE_EL1: + /* + * Trapped when the guest is using GICv2 whilst the platform + * interrupt controller is GICv3. In this case, the register + * should be emulate as RAZ/WI to tell the guest to use the GIC + * memory mapped interface (i.e GICv2 compatibility). + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* * HCR_EL2.TIDCP * * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h index 570f43e..887368e 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/sysregs.h @@ -90,6 +90,7 @@ #define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5) #define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6) #define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) +#define HSR_SYSREG_ICC_SRE_EL1 HSR_SYSREG(3,0,c12,c12,5) #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1) #define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0)