From patchwork Tue Aug 21 09:30:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 144694 Delivered-To: patch@linaro.org Received: by 2002:a50:c01b:0:0:0:0:0 with SMTP id r27-v6csp3022840edb; Tue, 21 Aug 2018 02:41:57 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzwN67JpCTh6AXneYocMw+dtAsyhH2HHHYoOzs7fTRrZqQ+ux53B5ekXB/MZw2/U7YAJGqe X-Received: by 2002:a17:902:9f86:: with SMTP id g6-v6mr17204901plq.304.1534844517619; Tue, 21 Aug 2018 02:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534844517; cv=none; d=google.com; s=arc-20160816; b=sSV2Rd1lHcu2pxLlnpBeik2u9PEUfNdki5atg7mm1txubNpb3MCW3xulf1wWXXK4nZ 7KQhwa17UJ0vPpjhNrAnj0FN9curovcXmNLQz8XJYaADRzm1FGwzpyOOxUQ1f5ZlEhio O87Qp3cNNUH0JNCQIWZJTBPfOcbjSyR3izrxVLfViT3lDlTQWNVSpDq1Fo6+CA/5c/Nm mU2zq07i2nYixv1aJvTixVnv2Ps1Vhwag9c9ObgXynqiLvwiXqKcssAK89oh1/LS3Ijo TNsCYsqZ4lba5CVokuceueTmmvO55I9MmGb4Y+/NipXSSC8Gqd0lseJwG7CEx6JY7H9M 6p0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=3OUPKJWTIxdaCtn7CTgl+g1OgM2VRTwed1lW1heA02o=; b=ud1zTFqIELFkjJvhNh8nL5itGpMG7dwIyWkEuhax466+8cPrg6y2at54tSEgJI24MV cfk+PSWHKEP/YNF9Fx8AFaggv6FLox1cbgb3NyLcTfwxgF5ZZzGWG8gkJeMivUBAGX/Q EuiGNzW3KqQizS603h+cnFHrx93F178XczLrR6ePhiUNo6LTyv2d0PyjOkc9lGy62zDM 6rD3rvj1LsqJcHpBnJ/kiWWlcY2NKt1miPrLz2H5AU0Ci/DLZUhi3EqFeHOueCJD7+3o rqzh46h8Ti+4Br4Vr1Xc2eEmCkAKlzcQM3otkNbGyQrwKR7kBglj4TqxVEh4laPy/piP 7rAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=oVhUBZQr; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 21-v6si11694354pgl.62.2018.08.21.02.41.57; Tue, 21 Aug 2018 02:41:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=oVhUBZQr; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726720AbeHUNA7 (ORCPT + 3 others); Tue, 21 Aug 2018 09:00:59 -0400 Received: from condef-09.nifty.com ([202.248.20.74]:22843 "EHLO condef-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726641AbeHUNA6 (ORCPT ); Tue, 21 Aug 2018 09:00:58 -0400 Received: from conuserg-12.nifty.com ([10.126.8.75])by condef-09.nifty.com with ESMTP id w7L9V8OZ011963 for ; Tue, 21 Aug 2018 18:31:10 +0900 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id w7L9UZgI008444; Tue, 21 Aug 2018 18:30:36 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w7L9UZgI008444 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1534843837; bh=3OUPKJWTIxdaCtn7CTgl+g1OgM2VRTwed1lW1heA02o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oVhUBZQrZW+tM5OFPnt+nFYB/iZc4Qy1bDy0abDydfC7g1UEi5inQTfmojP1j1Lo7 XSYWsmEiRv3Ui2ipIq/NEvX78bLS1fhqUtyXEofCoPwpmU3VW8+fbPpINKB9qx5Q39 72YynQYzKFZHlm+yYh223mg185fX53zsRN8o4Neqs6W/ScPcIkUkJSOpVwwNZXqswh sa4pHDKRxKeZklUhzhpMlZ98byNO19MhVlbdj7JUVtv/nSIQEMwxSKDGn1OogZofNC Ac/Owf0BxXGq6CUlNNBVHmXALScU8NgT578RouykDzujg6kS9g3n760omRMYLz6PLP A35EuAcHeRr5w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Vinod Koul , dmaengine@vger.kernel.org Cc: Masami Hiramatsu , Jassi Brar , Masahiro Yamada Subject: [PATCH 1/2] dt-bindings: dmaengine: add DT binding for UniPhier MIO DMAC Date: Tue, 21 Aug 2018 18:30:08 +0900 Message-Id: <1534843809-4137-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534843809-4137-1-git-send-email-yamada.masahiro@socionext.com> References: <1534843809-4137-1-git-send-email-yamada.masahiro@socionext.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4, Pro4, and sLD8 SoCs. Signed-off-by: Masahiro Yamada --- .../devicetree/bindings/dma/uniphier-mio-dmac.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt new file mode 100644 index 0000000..a9e969e --- /dev/null +++ b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt @@ -0,0 +1,28 @@ +UniPhier Media IO DMA controller + +This works as an external DMA engine for SD/eMMC controllers etc. +found in UniPhier LD4, Pro4, sLD8 SoCs. + +Required properties: +- compatible: should be "socionext,uniphier-mio-dmac". +- reg: offset and length of the register set for the device. +- interrupts: a list of interrupt specifiers associated with the DMA channels. +- clocks: a single clock specifier +- #dma-cells: should be <1>. The single cell represents the channel number. +- dma-channels: specify the number of the DMA channels. This should match to + the number of tuples in the interrupts property. + +Example: + dmac: dmac@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + #dma-cells = <1>; + dma-channels = <8>; + }; + +Note: +In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo. +The first two channels share a single interrupt line.