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[209.85.220.65]) by mx.google.com with SMTPS id k11sor7348562pfu.9.2020.07.10.06.12.41 for (Google Transport Security); Fri, 10 Jul 2020 06:12:42 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f0RW6sIN; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L5QBpzbQ08BmWVXWQQ1Ei99UM9wMUTbD0qwaSmoJOcI=; b=f0RW6sINEnRvP5/8ARWSnCe5qeicZ+JQkHNFbLZj3lYowZCL9XhqzcTt+ftQ7kH9Ae IqW+dFwpywuKLUYx4YKxuOoCioT6OCso9mQP/I9rgQjm0V6QaxbnbJus4i+6z+jqbnmC VwUaI7IGKoyFHj8dfAdqHgcS+Cn+lhbZ/2l4IqfNkj13dx+Tap4nu/2dCdbs8DgLyHrx /7aWjgm6y1HcpKtEaTF5JEcxQLBu4oQv8AVmj/uviX1icGJleWjxUEmcdlhrUwjg1RB4 GJzsKW7QZ+9uhbcawsYVmO7V+luaAi61EJnvE8kA5sw7ktCyF/6T3ByFVMLGHIcsOH4o fvTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L5QBpzbQ08BmWVXWQQ1Ei99UM9wMUTbD0qwaSmoJOcI=; b=R3KClf7ocr2hhorbsBBY767SynTDnDzq6UDEXhMSLdoLv+QYas7EYvbhZPJkKEUXns JqJPnmw5eKln/iPXOupV0Y+AXHdpy97ODRmIs6OQIhDO3Ct1d/hwq1fsaKZ7GK/xCgnP LjMqOSDeQHQ910PjGWfCHwTIAaBJOl+Xr6GN2hVqAWHtkxIDKQhwfffu66iHdrkIX8nx 6ndAYrkuGqU9D21p0bE6oKuIOCSjHdqpYkgF6KN715CCQegM9ieXL3waP4PFNbzFCtwI 4SRdUE4FPTW77RDAT74c45uToWalkZ2XAvXfANTVWXVwku1MAN3jMkP8p4x4PGM/iYuL mNLA== X-Gm-Message-State: AOAM5329PQ2NeD1Nt9YvEn4br9ibITPdepwTBV9T+pUtQsyEbDR59lIi GBuItoauC79LR0nHzZoLItqWPBP/6FVKgQ== X-Google-Smtp-Source: ABdhPJzm/WSpZzSCqxDz4d/6I4pf78uvBk1qbQUyLji0vwRD+v5PjGrCIL7tOXlzT113i8mQEssvQg== X-Received: by 2002:aa7:9303:: with SMTP id 3mr53508499pfj.108.1594386761414; Fri, 10 Jul 2020 06:12:41 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.210.211.230]) by smtp.gmail.com with ESMTPSA id d25sm5553279pgn.2.2020.07.10.06.12.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Jul 2020 06:12:40 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [RFC INTERNAL v2 3/4] serial: amba-pl011: Re-order APIs definition Date: Fri, 10 Jul 2020 18:42:04 +0530 Message-Id: <1594386725-10346-4-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594386725-10346-1-git-send-email-sumit.garg@linaro.org> References: <1594386725-10346-1-git-send-email-sumit.garg@linaro.org> Re-order pl011_hwinit() and pl011_enable_interrupts() APIs definition to allow their re-use in polling mode. Signed-off-by: Sumit Garg --- drivers/tty/serial/amba-pl011.c | 148 ++++++++++++++++++++-------------------- 1 file changed, 74 insertions(+), 74 deletions(-) -- 2.7.4 diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 8efd7c2..0983c5e 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -1581,6 +1581,80 @@ static void pl011_break_ctl(struct uart_port *port, int break_state) spin_unlock_irqrestore(&uap->port.lock, flags); } +static int pl011_hwinit(struct uart_port *port) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + int retval; + + /* Optionaly enable pins to be muxed in and configured */ + pinctrl_pm_select_default_state(port->dev); + + /* + * Try to enable the clock producer. + */ + retval = clk_prepare_enable(uap->clk); + if (retval) + return retval; + + uap->port.uartclk = clk_get_rate(uap->clk); + + /* Clear pending error and receive interrupts */ + pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | + UART011_FEIS | UART011_RTIS | UART011_RXIS, + uap, REG_ICR); + + /* + * Save interrupts enable mask, and enable RX interrupts in case if + * the interrupt is used for NMI entry. + */ + uap->im = pl011_read(uap, REG_IMSC); + pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); + + if (dev_get_platdata(uap->port.dev)) { + struct amba_pl011_data *plat; + + plat = dev_get_platdata(uap->port.dev); + if (plat->init) + plat->init(); + } + return 0; +} + +/* + * Enable interrupts, only timeouts when using DMA + * if initial RX DMA job failed, start in interrupt mode + * as well. + */ +static void pl011_enable_interrupts(struct uart_amba_port *uap) +{ + unsigned int i; + + spin_lock_irq(&uap->port.lock); + + /* Clear out any spuriously appearing RX interrupts */ + pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); + + /* + * RXIS is asserted only when the RX FIFO transitions from below + * to above the trigger threshold. If the RX FIFO is already + * full to the threshold this can't happen and RXIS will now be + * stuck off. Drain the RX FIFO explicitly to fix this: + */ + for (i = 0; i < uap->fifosize * 2; ++i) { + if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) + break; + + pl011_read(uap, REG_DR); + } + + uap->im = UART011_RTIM; + if (!pl011_dma_rx_running(uap)) + uap->im |= UART011_RXIM; + pl011_write(uap->im, uap, REG_IMSC); + spin_unlock_irq(&uap->port.lock); +} + #ifdef CONFIG_CONSOLE_POLL static void pl011_quiesce_irqs(struct uart_port *port) @@ -1639,46 +1713,6 @@ static void pl011_put_poll_char(struct uart_port *port, #endif /* CONFIG_CONSOLE_POLL */ -static int pl011_hwinit(struct uart_port *port) -{ - struct uart_amba_port *uap = - container_of(port, struct uart_amba_port, port); - int retval; - - /* Optionaly enable pins to be muxed in and configured */ - pinctrl_pm_select_default_state(port->dev); - - /* - * Try to enable the clock producer. - */ - retval = clk_prepare_enable(uap->clk); - if (retval) - return retval; - - uap->port.uartclk = clk_get_rate(uap->clk); - - /* Clear pending error and receive interrupts */ - pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | - UART011_FEIS | UART011_RTIS | UART011_RXIS, - uap, REG_ICR); - - /* - * Save interrupts enable mask, and enable RX interrupts in case if - * the interrupt is used for NMI entry. - */ - uap->im = pl011_read(uap, REG_IMSC); - pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); - - if (dev_get_platdata(uap->port.dev)) { - struct amba_pl011_data *plat; - - plat = dev_get_platdata(uap->port.dev); - if (plat->init) - plat->init(); - } - return 0; -} - static bool pl011_split_lcrh(const struct uart_amba_port *uap) { return pl011_reg_to_offset(uap, REG_LCRH_RX) != @@ -1707,40 +1741,6 @@ static int pl011_allocate_irq(struct uart_amba_port *uap) return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); } -/* - * Enable interrupts, only timeouts when using DMA - * if initial RX DMA job failed, start in interrupt mode - * as well. - */ -static void pl011_enable_interrupts(struct uart_amba_port *uap) -{ - unsigned int i; - - spin_lock_irq(&uap->port.lock); - - /* Clear out any spuriously appearing RX interrupts */ - pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); - - /* - * RXIS is asserted only when the RX FIFO transitions from below - * to above the trigger threshold. If the RX FIFO is already - * full to the threshold this can't happen and RXIS will now be - * stuck off. Drain the RX FIFO explicitly to fix this: - */ - for (i = 0; i < uap->fifosize * 2; ++i) { - if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) - break; - - pl011_read(uap, REG_DR); - } - - uap->im = UART011_RTIM; - if (!pl011_dma_rx_running(uap)) - uap->im |= UART011_RXIM; - pl011_write(uap->im, uap, REG_IMSC); - spin_unlock_irq(&uap->port.lock); -} - static int pl011_startup(struct uart_port *port) { struct uart_amba_port *uap =