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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id 1sm1721198wmj.35.2018.03.09.07.11.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 07:11:55 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Fri, 9 Mar 2018 15:11:28 +0000 Message-Id: <20180309151133.31371-13-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180309151133.31371-1-andre.przywara@linaro.org> References: <20180309151133.31371-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 12/17] ARM: VGIC: Introduce gic_get_nr_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far the number of list registers (LRs) a GIC implements is only needed in the hardware facing side of the VGIC code (gic-vgic.c). The new VGIC will need this information in more and multiple places, so export a function that returns the number. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/gic-vgic.c | 10 +++++----- xen/include/asm-arm/gic.h | 6 ++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index f4c98bffd1..61f093db50 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -25,7 +25,7 @@ #include #include -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) #undef GIC_DEBUG @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); struct gic_lr lr_val; @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); struct pending_irq *p = irq_to_pending(v, virtual_irq); ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -251,7 +251,7 @@ void vgic_sync_from_lrs(struct vcpu *v) { int i = 0; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); /* The idle domain has no LRs to be cleared. Since gic_restore_state * doesn't write any LR registers for the idle domain they could be @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); int lrs = nr_lrs; spin_lock_irqsave(&v->arch.vgic.lock, flags); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index ff0b22451b..49cb94f792 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -374,6 +374,12 @@ struct gic_hw_operations { }; extern const struct gic_hw_operations *gic_hw_ops; + +static inline unsigned int gic_get_nr_lrs(void) +{ + return gic_hw_ops->info->nr_lrs; +} + void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic,