Message ID | 20180315203050.19791-37-andre.przywara@linaro.org |
---|---|
State | Superseded |
Headers | show
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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:45 -0700 (PDT) From: Andre Przywara <andre.przywara@linaro.org> To: Stefano Stabellini <sstabellini@kernel.org>, Julien Grall <julien.grall@arm.com> Date: Thu, 15 Mar 2018 20:30:41 +0000 Message-Id: <20180315203050.19791-37-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 36/45] ARM: new VGIC: Dump virtual IRQ info X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion <xen-devel.lists.xenproject.org> List-Unsubscribe: <https://lists.xenproject.org/mailman/options/xen-devel>, <mailto:xen-devel-request@lists.xenproject.org?subject=unsubscribe> List-Post: <mailto:xen-devel@lists.xenproject.org> List-Help: <mailto:xen-devel-request@lists.xenproject.org?subject=help> List-Subscribe: <https://lists.xenproject.org/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xenproject.org?subject=subscribe> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" <xen-devel-bounces@lists.xenproject.org> |
Series |
New VGIC(-v2) implementation
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expand
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diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index d7ef6e32fc..b56682f8e4 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -756,6 +756,31 @@ void vgic_free_virq(struct domain *d, unsigned int virq) clear_bit(virq, d->arch.vgic.allocated_irqs); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct vgic_cpu *vgic_cpu = &v->arch.vgic; + struct vgic_irq *irq; + unsigned long flags; + + spin_lock_irqsave(&v->arch.vgic.ap_list_lock, flags); + + if ( !list_empty(&vgic_cpu->ap_list_head) ) + printk(" active or pending interrupts queued:\n"); + + list_for_each_entry ( irq, &vgic_cpu->ap_list_head, ap_list ) + { + spin_lock(&irq->irq_lock); + printk(" %s %s irq %u: %spending, %sactive, %senabled\n", + irq->hw ? "hardware" : "virtual", + irq->config == VGIC_CONFIG_LEVEL ? "level" : "edge", + irq->intid, irq_is_pending(irq) ? "" : "not ", + irq->active ? "" : "not ", irq->enabled ? "" : "not "); + spin_unlock(&irq->irq_lock); + } + + spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) {