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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:22 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:29 +0000 Message-Id: <20180321163235.12529-34-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 33/39] ARM: new VGIC: Add preliminary stub implementation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM arch code requires an interrupt controller emulation to implement vgic_clear_pending_irqs(), although it is suspected that it is actually not necessary. Go with a stub for now to make the linker happy. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 23b8abfc5e..b70fdaaecb 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -791,6 +791,14 @@ void gic_dump_vgic_info(struct vcpu *v) spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); } +void vgic_clear_pending_irqs(struct vcpu *v) +{ + /* + * TODO: It is unclear whether we really need this, so we might instead + * remove it on the caller site. + */ +} + /** * arch_move_irqs() - migrate the physical affinity of hardware mapped vIRQs * @v: the vCPU, already assigned to the new pCPU