From patchwork Wed May 8 16:15:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 163632 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp2885501ilm; Wed, 8 May 2019 09:17:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqxC1WzW/UV1E7/0qPl3cbmd5PHVMow90KJFiHO8GaZm1OfdF4pyF1iCgjs7tOF+tgnzFRVF X-Received: by 2002:a6b:400a:: with SMTP id k10mr2891659ioa.291.1557332259087; Wed, 08 May 2019 09:17:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557332259; cv=none; d=google.com; s=arc-20160816; b=VEt5emt/ticioXBzhzqN2nKa2DJYwX2dwpYDG6Z4NTLpD629+1b2BF44JWu3jyRXe7 TarqGsk54vIebTAkLtxWovnBXEfcJvZCrjpxXOinavJc2AWChf3rs3uAEeLzuofYG24G Uk2bRp3LUn+VvYbtFpjLUzBfFE+8esvL+VxOKML32xcjCRNa4BLE0x7dsv3/5q2s4W0P yQjk8bLtWkLpak1twQLYSynN3Jc9TQ4QrI4HCrrMq7DLQbvcMkuQxno4oEjVVtzjbLUc 4fAq6FXIf4cfvk3izKKxLyUA8Z9s695f/5dJ1QCcOLxvKu3H3mxvlKRCtODzmjVBePVX krAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=NoZMvxkSkprMe5xAdHfiM6TdqLi/731CfK3ogVRKyJs=; b=A320iKEPr5ri6v06zFl30Bo0iVznbk9XkPB0FFTcO0Dij6B1NJ22YhQyXBjfu3PAXl FfF11urSws4X5HFL1S2xEz6YV8XAwv6UwHAekuHH754oJfrwf/G0Iu83y0l+/7erIDxB qP1yt/yv2+RkZ3/A2M6Fz8ufN8D0mZPdwktcEJ7d1spqu4sexLz3M3rTF7vZFQm56fRt YbQCg4NiGDww4kY3UiXo0iuUObYx80YE1iNpdqYFmSYtwpDshOFyZv3SRJ8FAP3AmySL 5GtW3TDU/JHgFI+Fa0g8Vj3nLi9I6m8NuT7hmsG2R66BUJo1CLYvEQ5Ddk2MKuAPJjUV CTtA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t11si2228234itb.34.2019.05.08.09.17.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 May 2019 09:17:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hOPEs-0008Ez-Cf; Wed, 08 May 2019 16:16:14 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hOPEq-0008Eg-JT for xen-devel@lists.xenproject.org; Wed, 08 May 2019 16:16:12 +0000 X-Inumbo-ID: 9839b0ba-71ac-11e9-843c-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 9839b0ba-71ac-11e9-843c-bc764e045a96; Wed, 08 May 2019 16:16:11 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32B5815AB; Wed, 8 May 2019 09:16:11 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F3A763F238; Wed, 8 May 2019 09:16:09 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Wed, 8 May 2019 17:15:58 +0100 Message-Id: <20190508161603.21964-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190508161603.21964-1-julien.grall@arm.com> References: <20190508161603.21964-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 2/7] xen/arm: Remove flush_xen_text_tlb_local() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function flush_xen_text_tlb_local() has been misused and will result to invalidate the instruction cache more than necessary. For instance, there are no need to invalidate the instruction cache if we are setting SCTLR_EL2.WXN. There are effectively only one caller (i.e free_init_memory() would who need to invalidate the instruction cache. So rather than keeping around the function flush_xen_text_tlb_local() around, replace it with call to flush_xen_tlb_local() and explicitely flush the cache when necessary. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 17 ++++++++++++++--- xen/include/asm-arm/arm32/page.h | 23 +++++++++-------------- xen/include/asm-arm/arm64/page.h | 21 +++++---------------- 3 files changed, 28 insertions(+), 33 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 93ad118183..dfbe39c70a 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -610,8 +610,12 @@ void __init remove_early_mappings(void) static void xen_pt_enforce_wnx(void) { WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); - /* Flush everything after setting WXN bit. */ - flush_xen_text_tlb_local(); + /* + * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized + * before flushing the TLBs. + */ + isb(); + flush_xen_data_tlb_local(); } extern void switch_ttbr(uint64_t ttbr); @@ -1123,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg) } write_pte(xen_xenmap + i, pte); } - flush_xen_text_tlb_local(); + flush_xen_data_tlb_local(); } /* Release all __init and __initdata ranges to be reused */ @@ -1136,6 +1140,13 @@ void free_init_memory(void) uint32_t *p; set_pte_flags_on_range(__init_begin, len, mg_rw); + + /* + * From now on, init will not be used for execution anymore, + * so nuke the instruction cache to remove entries related to init. + */ + invalidate_icache_local(); + #ifdef CONFIG_ARM_32 /* udf instruction i.e (see A8.8.247 in ARM DDI 0406C.c) */ insn = 0xe7f000f0; diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index ea4b312c70..40a77daa9d 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -46,24 +46,19 @@ static inline void invalidate_icache(void) } /* - * Flush all hypervisor mappings from the TLB and branch predictor of - * the local processor. - * - * This is needed after changing Xen code mappings. - * - * The caller needs to issue the necessary DSB and D-cache flushes - * before calling flush_xen_text_tlb. + * Invalidate all instruction caches on the local processor to PoU. + * We also need to flush the branch predictor for ARMv7 as it may be + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b). */ -static inline void flush_xen_text_tlb_local(void) +static inline void invalidate_icache_local(void) { asm volatile ( - "isb;" /* Ensure synchronization with previous changes to text */ - CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */ - CMD_CP32(ICIALLU) /* Flush I-cache */ - CMD_CP32(BPIALL) /* Flush branch predictor */ - "dsb;" /* Ensure completion of TLB+BP flush */ - "isb;" + CMD_CP32(ICIALLU) /* Flush I-cache. */ + CMD_CP32(BPIALL) /* Flush branch predictor. */ : : : "memory"); + + dsb(nsh); /* Ensure completion of the flush I-cache */ + isb(); /* Synchronize fetched instruction stream. */ } /* diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 23d778154d..6c36d0210f 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -37,23 +37,12 @@ static inline void invalidate_icache(void) isb(); } -/* - * Flush all hypervisor mappings from the TLB of the local processor. - * - * This is needed after changing Xen code mappings. - * - * The caller needs to issue the necessary DSB and D-cache flushes - * before calling flush_xen_text_tlb. - */ -static inline void flush_xen_text_tlb_local(void) +/* Invalidate all instruction caches on the local processor to PoU */ +static inline void invalidate_icache_local(void) { - asm volatile ( - "isb;" /* Ensure synchronization with previous changes to text */ - "tlbi alle2;" /* Flush hypervisor TLB */ - "ic iallu;" /* Flush I-cache */ - "dsb sy;" /* Ensure completion of TLB flush */ - "isb;" - : : : "memory"); + asm volatile ("ic iallu"); + dsb(nsh); /* Ensure completion of the I-cache flush */ + isb(); } /*