From patchwork Tue May 14 12:21:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164171 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552267ili; Tue, 14 May 2019 05:23:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqw5FMmevZ/RqqFbezRY/wxleg2hKzMaiuyqS7Hc8q1HsuRyutXcOjh/xnk7iv3OZwTj6/Yp X-Received: by 2002:a6b:7941:: with SMTP id j1mr19167552iop.177.1557836597147; Tue, 14 May 2019 05:23:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836597; cv=none; d=google.com; s=arc-20160816; b=I+HthXk8z0MYL1ucgiaY6JcLS098LtgQ/DT0E0dgD5C/q0V2YSOlJMtls5g1Aeyu9y 5qJ0F+EjvbW83mL4gLBju9el5QnSXDQsx6+bebHb5xZ2ggob8TlOc+4DV/l5tan7usr2 OgZ0/H6Lk7XYyPjk6IOqXIf0oc2hVl7s2D17VMk1dCIV88LUOBTgwSUilrmSYcVliiZt ZlRnpW+gLP+uKx4rfEHEFzGLJKbzlt+7YxJShM1kUXygutrX3bYmL7uo9dMIVCXpVkXO 89UpquJOHgnDS5UZ8baFiRylrIrqteGMpUbIBSFq09sIstEcMhFVTB4wnsz3GmF8rhI+ BgpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=/DjATLLwijxVHadIgyWn5FkdAlOqBTmWKIEUArYxpTU=; b=mP0FlezocJNpOn5KRWSJvIEKaevXgF4+YIc1Q/Pab0oJ0n3nutrU6L5gYZR9w+tsGY VajOjEhZbo6KX9TROG5lGFE98MwGbAWjXqAsHIiR9LoT12dC0ktaw8D7iKdkuNTqENal Ddpl5FwXyFBqsl4HuPc4BbYw3+Pd+iC1aaPUR1vsRdPVz9kgrC19bub28UvQCFP46/hb 311Nys8/3O5l17ZRmPZVmCEISdCIRY6xUJGjLXl88urrC4DgiO3TJbmljj+wM1mXWdbR KvIge7XHZ9P/4OJ+kJFbfYGXKPZrewnurmgDZSIWhLzwQhJQL8pPI6KCBcVHedkZ1BSw jPQw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n129si1420215itb.61.2019.05.14.05.23.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRO-00089L-C5; Tue, 14 May 2019 12:21:54 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRN-00088h-7M for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:21:53 +0000 X-Inumbo-ID: da83c45e-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id da83c45e-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:21:51 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98A37341; Tue, 14 May 2019 05:21:51 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 890773F71E; Tue, 14 May 2019 05:21:50 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:14 +0100 Message-Id: <20190514122136.28215-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 03/19] xen/arm: processor: Use BIT(.., UL) instead of _AC(1, U) in SCTLR_ defines X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Use the pattern BIT(..., UL) to make the code more readable. Note that unsigned long is used instead of unsigned because SCTLR is technically 32-bit on Arm32 and 64-bit on Arm64. Signed-off-by: Julien Grall --- Changes in v2: - Rework the patch to use BIT(..., UL) instead of _BITUL(...). --- xen/include/asm-arm/processor.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index f3b68185eb..bbcba061ca 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -120,20 +120,20 @@ /* Bits specific to SCTLR_EL1 for Arm32 */ -#define SCTLR_A32_EL1_V (_AC(1,U)<<13) +#define SCTLR_A32_EL1_V BIT(13, UL) /* Common bits for SCTLR_ELx for Arm32 */ -#define SCTLR_A32_ELx_TE (_AC(1,U)<<30) -#define SCTLR_A32_ELx_FI (_AC(1,U)<<21) +#define SCTLR_A32_ELx_TE BIT(30, UL) +#define SCTLR_A32_ELx_FI BIT(21, UL) /* Common bits for SCTLR_ELx on all architectures */ -#define SCTLR_Axx_ELx_EE (_AC(1,U)<<25) -#define SCTLR_Axx_ELx_WXN (_AC(1,U)<<19) -#define SCTLR_Axx_ELx_I (_AC(1,U)<<12) -#define SCTLR_Axx_ELx_C (_AC(1,U)<<2) -#define SCTLR_Axx_ELx_A (_AC(1,U)<<1) -#define SCTLR_Axx_ELx_M (_AC(1,U)<<0) +#define SCTLR_Axx_ELx_EE BIT(25, UL) +#define SCTLR_Axx_ELx_WXN BIT(19, UL) +#define SCTLR_Axx_ELx_I BIT(12, UL) +#define SCTLR_Axx_ELx_C BIT(2, UL) +#define SCTLR_Axx_ELx_A BIT(1, UL) +#define SCTLR_Axx_ELx_M BIT(0, UL) #define HSCTLR_BASE _AC(0x30c51878,U)