| Message ID | 20190514122456.28559-4-julien.grall@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | xen/arm: Clean-up & fixes in boot/mm code | expand |
On Tue, 14 May 2019, Julien Grall wrote: > Use the pattern BIT(..., UL) to make the code more readable. Note that > unsigned long is used instead of unsigned because SCTLR is technically > 32-bit on Arm32 and 64-bit on Arm64. > > Signed-off-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v2: > - Rework the patch to use BIT(..., UL) instead of _BITUL(...). > --- > xen/include/asm-arm/processor.h | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index f3b68185eb..bbcba061ca 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -120,20 +120,20 @@ > > /* Bits specific to SCTLR_EL1 for Arm32 */ > > -#define SCTLR_A32_EL1_V (_AC(1,U)<<13) > +#define SCTLR_A32_EL1_V BIT(13, UL) > > /* Common bits for SCTLR_ELx for Arm32 */ > > -#define SCTLR_A32_ELx_TE (_AC(1,U)<<30) > -#define SCTLR_A32_ELx_FI (_AC(1,U)<<21) > +#define SCTLR_A32_ELx_TE BIT(30, UL) > +#define SCTLR_A32_ELx_FI BIT(21, UL) > > /* Common bits for SCTLR_ELx on all architectures */ > -#define SCTLR_Axx_ELx_EE (_AC(1,U)<<25) > -#define SCTLR_Axx_ELx_WXN (_AC(1,U)<<19) > -#define SCTLR_Axx_ELx_I (_AC(1,U)<<12) > -#define SCTLR_Axx_ELx_C (_AC(1,U)<<2) > -#define SCTLR_Axx_ELx_A (_AC(1,U)<<1) > -#define SCTLR_Axx_ELx_M (_AC(1,U)<<0) > +#define SCTLR_Axx_ELx_EE BIT(25, UL) > +#define SCTLR_Axx_ELx_WXN BIT(19, UL) > +#define SCTLR_Axx_ELx_I BIT(12, UL) > +#define SCTLR_Axx_ELx_C BIT(2, UL) > +#define SCTLR_Axx_ELx_A BIT(1, UL) > +#define SCTLR_Axx_ELx_M BIT(0, UL) > > #define HSCTLR_BASE _AC(0x30c51878,U) > > -- > 2.11.0 >
On 14.05.19 15:24, Julien Grall wrote: > Use the pattern BIT(..., UL) to make the code more readable. Note that > unsigned long is used instead of unsigned because SCTLR is technically > 32-bit on Arm32 and 64-bit on Arm64. > > Signed-off-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index f3b68185eb..bbcba061ca 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -120,20 +120,20 @@ /* Bits specific to SCTLR_EL1 for Arm32 */ -#define SCTLR_A32_EL1_V (_AC(1,U)<<13) +#define SCTLR_A32_EL1_V BIT(13, UL) /* Common bits for SCTLR_ELx for Arm32 */ -#define SCTLR_A32_ELx_TE (_AC(1,U)<<30) -#define SCTLR_A32_ELx_FI (_AC(1,U)<<21) +#define SCTLR_A32_ELx_TE BIT(30, UL) +#define SCTLR_A32_ELx_FI BIT(21, UL) /* Common bits for SCTLR_ELx on all architectures */ -#define SCTLR_Axx_ELx_EE (_AC(1,U)<<25) -#define SCTLR_Axx_ELx_WXN (_AC(1,U)<<19) -#define SCTLR_Axx_ELx_I (_AC(1,U)<<12) -#define SCTLR_Axx_ELx_C (_AC(1,U)<<2) -#define SCTLR_Axx_ELx_A (_AC(1,U)<<1) -#define SCTLR_Axx_ELx_M (_AC(1,U)<<0) +#define SCTLR_Axx_ELx_EE BIT(25, UL) +#define SCTLR_Axx_ELx_WXN BIT(19, UL) +#define SCTLR_Axx_ELx_I BIT(12, UL) +#define SCTLR_Axx_ELx_C BIT(2, UL) +#define SCTLR_Axx_ELx_A BIT(1, UL) +#define SCTLR_Axx_ELx_M BIT(0, UL) #define HSCTLR_BASE _AC(0x30c51878,U)
Use the pattern BIT(..., UL) to make the code more readable. Note that unsigned long is used instead of unsigned because SCTLR is technically 32-bit on Arm32 and 64-bit on Arm64. Signed-off-by: Julien Grall <julien.grall@arm.com> --- Changes in v2: - Rework the patch to use BIT(..., UL) instead of _BITUL(...). --- xen/include/asm-arm/processor.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)