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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id 131sm6493221pge.37.2019.08.30.22.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 22:23:26 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Fri, 30 Aug 2019 22:23:12 -0700 Message-Id: <20190831052314.19974-2-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190831052314.19974-1-raj.khem@gmail.com> References: <20190831052314.19974-1-raj.khem@gmail.com> MIME-Version: 1.0 Subject: [OE-core] [PATCH 2/4] tune-riscv: Drop littleendian and introduce bigendian tune X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Default riscv is little-endian moreover most of other arches define bigendian as tune and treats absense as litteendian, this make risc-v fall in line Signed-off-by: Khem Raj --- meta/conf/machine/include/riscv/tune-riscv.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 1e3a1081e0..25d0463492 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -3,16 +3,16 @@ require conf/machine/include/riscv/arch-riscv.inc TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations" TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations" -TUNEVALID[littleendian] = "Little endian mode" +TUNEVALID[bigendian] = "Big endian mode" AVAILTUNES += "riscv64 riscv32" -TUNE_FEATURES_tune-riscv64 = "riscv64 littleendian" +TUNE_FEATURES_tune-riscv64 = "riscv64" TUNE_ARCH_tune-riscv64 = "riscv64" TUNE_PKGARCH_tune-riscv64 = "riscv64" PACKAGE_EXTRA_ARCHS_tune-riscv64 = "riscv64" -TUNE_FEATURES_tune-riscv32 = "riscv32 littleendian" +TUNE_FEATURES_tune-riscv32 = "riscv32" TUNE_ARCH_tune-riscv32 = "riscv32" TUNE_PKGARCH_tune-riscv32 = "riscv32" PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"