[08/10] gcc-runtime: Disable libitm on riscv

Message ID	42e0f32bced9a1a9933a856732c68497324eb0ff.1507250774.git.raj.khem@gmail.com
State	Accepted
Commit	21caa8bcda93ce67ef58548f7b85d0569d13d0b9
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) client-ip=140.211.169.62; From: Khem Raj <raj.khem@gmail.com> To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:47 -0700 Message-Id: <42e0f32bced9a1a9933a856732c68497324eb0ff.1507250774.git.raj.khem@gmail.com> In-Reply-To: <cover.1507250774.git.raj.khem@gmail.com> References: <cover.1507250774.git.raj.khem@gmail.com> Subject: [OE-core] [PATCH 08/10] gcc-runtime: Disable libitm on riscv Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org
Series	Add foundation for riscv architecture \| expand [00/10] Add foundation for riscv architecture [01/10] site: Add riscv32 and riscv64 [02/10] insane: Add entries for riscv 32bit/64bit [03/10] siteinfo: Define data for riscv32 and riscv64 [04/10] kernel-arch.bbclass: Add riscv to kernel arch map [05/10] runqemu: Add riscv support for qemu machines [06/10] binutils: Convert SRC_URI and SRCREV to weak defines [07/10] gcc: Backport fix for a segfault on riscv [08/10] gcc-runtime: Disable libitm on riscv [09/10] elfutils: Fix missing library on linker cmdline [10/10] openssl: Add support for riscv32/riscv64

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42e0f32bced9a1a9933a856732c68497324eb0ff.1507250774.git.raj.khem@gmail.com

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Accepted

Commit

21caa8bcda93ce67ef58548f7b85d0569d13d0b9

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From: Khem Raj <raj.khem@gmail.com>
To: openembedded-core@lists.openembedded.org
Date: Thu,  5 Oct 2017 17:50:47 -0700
Message-Id: <42e0f32bced9a1a9933a856732c68497324eb0ff.1507250774.git.raj.khem@gmail.com>
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Subject: [OE-core] [PATCH 08/10] gcc-runtime: Disable libitm on riscv
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Series

Add foundation for riscv architecture | expand

Commit Message

Khem Raj Oct. 6, 2017, 12:50 a.m. UTC

Signed-off-by: Khem Raj <raj.khem@gmail.com>

---
 meta/recipes-devtools/gcc/gcc-runtime.inc | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.14.2

-- 
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diff --git a/meta/recipes-devtools/gcc/gcc-runtime.inc b/meta/recipes-devtools/gcc/gcc-runtime.inc
index ee08529a5f..d3d4bd36a8 100644
--- a/meta/recipes-devtools/gcc/gcc-runtime.inc
+++ b/meta/recipes-devtools/gcc/gcc-runtime.inc
@@ -20,6 +20,8 @@  RUNTIMELIBITM = "libitm"
 RUNTIMELIBITM_mipsarch = ""
 RUNTIMELIBITM_nios2 = ""
 RUNTIMELIBITM_microblaze = ""
+RUNTIMELIBITM_riscv32 = ""
+RUNTIMELIBITM_riscv64 = ""
 
 RUNTIMETARGET = "libssp libstdc++-v3 libgomp libatomic ${RUNTIMELIBITM} \
     ${@bb.utils.contains_any('FORTRAN', [',fortran',',f77'], 'libquadmath', '', d)} \