From patchwork Thu Dec 8 12:41:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 5539 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5068823E04 for ; Thu, 8 Dec 2011 12:41:18 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 381C5A181CF for ; Thu, 8 Dec 2011 12:41:18 +0000 (UTC) Received: by bke17 with SMTP id 17so2162680bke.11 for ; Thu, 08 Dec 2011 04:41:18 -0800 (PST) Received: by 10.204.156.208 with SMTP id y16mr1343586bkw.72.1323348077839; Thu, 08 Dec 2011 04:41:17 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs92614bkc; Thu, 8 Dec 2011 04:41:17 -0800 (PST) Received: by 10.204.146.79 with SMTP id g15mr1264980bkv.121.1323348077354; Thu, 08 Dec 2011 04:41:17 -0800 (PST) Received: from mail-bw0-f50.google.com (mail-bw0-f50.google.com [209.85.214.50]) by mx.google.com with ESMTPS id ab2si1055448bkc.110.2011.12.08.04.41.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Dec 2011 04:41:17 -0800 (PST) Received-SPF: neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.214.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by bkcik5 with SMTP id ik5so1929837bkc.37 for ; Thu, 08 Dec 2011 04:41:16 -0800 (PST) Received: by 10.180.92.41 with SMTP id cj9mr5073345wib.21.1323348076448; Thu, 08 Dec 2011 04:41:16 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id b5sm8487058wbh.4.2011.12.08.04.41.15 (version=SSLv3 cipher=OTHER); Thu, 08 Dec 2011 04:41:15 -0800 (PST) From: Dave Martin To: patches@arm.linux.org.uk Cc: patches@linaro.org, Dave Martin Subject: [PATCH] ARM: errata: Remove SMP dependency for erratum 751472 Date: Thu, 8 Dec 2011 12:41:06 +0000 Message-Id: <1323348066-29602-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 Activation conditions for a workaround should not be encoded in the workaround's direct dependencies if this makes otherwise reasonable configuration choices impossible. This patches uses the SMP/UP patching facilities instead to compile out the workaround if the configuration means that it is definitely not needed. This means that configs for buggy silicon can simply select ARM_ERRATA_751472, without preventing a UP kernel from being built or duplicatiing knowledge about when to activate the workaround. This seems the correct way to do things, because the erratum is a property of the silicon, irrespective of what the kernel config happens to be. Signed-off-by: Dave Martin --- KernelVersion: v3.2-rc3 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 44789ef..e5bbb2f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1281,7 +1281,7 @@ config ARM_ERRATA_743622 config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" - depends on CPU_V7 && SMP + depends on CPU_V7 help This option enables the workaround for the 751472 Cortex-A9 (prior to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 2c559ac..e70a737 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -363,11 +363,13 @@ __v7_setup: orreq r10, r10, #1 << 6 @ set bit #6 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif -#ifdef CONFIG_ARM_ERRATA_751472 - cmp r6, #0x30 @ present prior to r3p0 +#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) + ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 + ALT_UP_B(1f) mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register orrlt r10, r10, #1 << 11 @ set bit #11 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +1: #endif 3: mov r10, #0