From patchwork Thu Jul 5 16:48:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9856 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 70DA123E16 for ; Thu, 5 Jul 2012 16:48:44 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3082CA181D9 for ; Thu, 5 Jul 2012 16:48:44 +0000 (UTC) Received: by yenq6 with SMTP id q6so8232213yen.11 for ; Thu, 05 Jul 2012 09:48:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=WWVavufmyXEjSFJNz3ETftcsj9RBAJUmBHmgIbZ2Iv8=; b=eMPz07VFnzybYXuAHcR8TaiWZfIC3AYTzMqVlwoEIQytF7JoF9o92+J3XBYndClJOm ugBJP01MKZtL2RCroP+z+UyH7mPkfF3pUiEBGM/4n1bXFp7JKJCQhKF/3g96zs8OJAWU ajdFKXJdHpBg1guLBAolFSOZ/F+HkP2nRd1kNZiJ8hkRV90PE3CP36uOTgjgm7KzG1hn 18yxo6yiw74ceJJSjuwZoZACQ+RGDId/wBA523D16t3EivxlQB0mmpcq9GQq9QxR4Oil VxemJgNigNxg0Ywv8V9+AIWP0jCJUvzilxbm2sDCINW4NIHbnwB7FLgt0hYMnykiLCLu I32A== Received: by 10.50.163.99 with SMTP id yh3mr280324igb.53.1341506923356; Thu, 05 Jul 2012 09:48:43 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp68225ibb; Thu, 5 Jul 2012 09:48:42 -0700 (PDT) Received: by 10.180.99.232 with SMTP id et8mr852217wib.11.1341506922235; Thu, 05 Jul 2012 09:48:42 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id ga1si1109327wib.44.2012.07.05.09.48.41 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Jul 2012 09:48:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SmpEM-0005kW-TR; Thu, 05 Jul 2012 17:48:38 +0100 From: Peter Maydell To: linaro-dev@lists.linaro.org Cc: patches@linaro.org, Grant Likely , Marc Zyngier , Dave Martin Subject: [PATCH] arm: Handle device tree memory regions larger than 4GB Date: Thu, 5 Jul 2012 17:48:38 +0100 Message-Id: <1341506918-22077-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQlvQL+85nHsCHzSWf3NUL36zBGc8e9FFJjOBK5OZnPRY6cXw4nwXJ3P7xv039Nd1IAcDnQQ Device tree memory regions may have sizes larger than 4GB. Instead of silently truncating a 64 bit size when we pass it to arm_add_memory(), split large regions into 2GB chunks. Signed-off-by: Peter Maydell --- With this patch, I can take a device tree which has been tweaked so its #address-cells and #size-cells are both 2, and boot it on a QEMU vexpress-a15 model with >4GB of RAM, and have the kernel actually detect the right amount of RAM. [the qemu bit needs some patches I haven't posted yet.] Since I'm not really a kernel dev I thought I'd post this to linaro-dev first in the hope of a bit of friendly local review before venturing onto lkml :-) (Apologies to those on cc who got this twice because I mistyped the linaro-dev email address.) arch/arm/kernel/devtree.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index bee7f9d..79a6e66 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -26,6 +26,11 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) { + while (size > 0x80000000) { + arm_add_memory(base, 0x80000000); + base += 0x80000000; + size -= 0x80000000; + } arm_add_memory(base, size); }