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Sat, 18 May 2013 12:08:14 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400e:c00::22d is neither permitted nor denied by best guess record for domain of sanjay.rawat@linaro.org) client-ip=2607:f8b0:400e:c00::22d; Received: by mail-da0-f45.google.com with SMTP id w3so3048707dad.18 for ; Sat, 18 May 2013 12:08:13 -0700 (PDT) X-Received: by 10.66.230.228 with SMTP id tb4mr28258048pac.160.1368904093917; Sat, 18 May 2013 12:08:13 -0700 (PDT) Received: from localhost.localdomain ([223.239.140.180]) by mx.google.com with ESMTPSA id ri8sm16685627pbc.3.2013.05.18.12.08.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 18 May 2013 12:08:13 -0700 (PDT) From: Sanjay Singh Rawat To: linaro-dev@lists.linaro.org Cc: patches@linaro.org, Sanjay Singh Rawat Subject: [RFC PATCH 1/6] ARM: cpuhotplug: add common hotplug related functions Date: Sun, 19 May 2013 00:38:18 +0530 Message-Id: <1368904103-22122-2-git-send-email-sanjay.rawat@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368904103-22122-1-git-send-email-sanjay.rawat@linaro.org> References: <1368904103-22122-1-git-send-email-sanjay.rawat@linaro.org> X-Gm-Message-State: ALoCoQmkhg5pMh7Uic3IxG+LACJAbifS66EcjzhszPwrs1ktkH+572fyokyI45wj7q4G5Ck3F9zs X-Original-Sender: sanjay.rawat@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::229 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add function which prepare arm processors to enter the low power for hotplug functionality and handle the return path. Signed-off-by: Sanjay Singh Rawat --- arch/arm/include/asm/hotplug.h | 19 ++++++++++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cpuhotplug.c | 64 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) create mode 100644 arch/arm/include/asm/hotplug.h create mode 100644 arch/arm/kernel/cpuhotplug.c diff --git a/arch/arm/include/asm/hotplug.h b/arch/arm/include/asm/hotplug.h new file mode 100644 index 0000000..340e438 --- /dev/null +++ b/arch/arm/include/asm/hotplug.h @@ -0,0 +1,19 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#if defined(CONFIG_HOTPLUG_CPU) +extern inline void cpu_enter_lowpower(void); +extern inline void cpu_leave_lowpower(void); +#else +static inline void cpu_enter_lowpower(void) +{ + return -ENODEV; +} +static inline void cpu_leave_lowpower(void) +{ + return -ENODEV; +} +#endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5f3338e..9bd370b 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o +obj-$(CONFIG_HOTPLUG_CPU) += cpuhotplug.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o diff --git a/arch/arm/kernel/cpuhotplug.c b/arch/arm/kernel/cpuhotplug.c new file mode 100644 index 0000000..8651b96 --- /dev/null +++ b/arch/arm/kernel/cpuhotplug.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +/* + * For Cortex-A9 processor + */ +static inline void ca9_enter_lowpower(void) +{ + unsigned int v; + + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %3\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +void cpu_enter_lowpower(void) +{ + int id = 0; + + /* check the cpuid */ + asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(id) : : "cc"); + + if ((id & 0xffffffff) == 0x411fc090) + ca9_enter_lowpower(); + else + pr_warn(KERN_WARNING "Unknown CPU type\n"); +}