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[216.34.181.88]) by mx.google.com with ESMTPS id f84si9766897ioj.14.2015.03.30.12.14.36 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 30 Mar 2015 12:14:37 -0700 (PDT) Received-SPF: pass (google.com: domain of edk2-devel-bounces@lists.sourceforge.net designates 216.34.181.88 as permitted sender) client-ip=216.34.181.88; Received: from localhost ([127.0.0.1] helo=sfs-ml-1.v29.ch3.sourceforge.com) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1Ycf8l-0003ma-Sv; Mon, 30 Mar 2015 19:14:27 +0000 Received: from sog-mx-1.v43.ch3.sourceforge.com ([172.29.43.191] helo=mx.sourceforge.net) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1Ycf8k-0003mQ-Fn for edk2-devel@lists.sourceforge.net; Mon, 30 Mar 2015 19:14:26 +0000 Received-SPF: pass (sog-mx-1.v43.ch3.sourceforge.com: domain of linaro.org designates 209.85.212.170 as permitted sender) client-ip=209.85.212.170; envelope-from=ard.biesheuvel@linaro.org; helo=mail-wi0-f170.google.com; Received: from mail-wi0-f170.google.com ([209.85.212.170]) by sog-mx-1.v43.ch3.sourceforge.com with esmtps (TLSv1:RC4-SHA:128) (Exim 4.76) id 1Ycf8j-0003Wt-0r for edk2-devel@lists.sourceforge.net; Mon, 30 Mar 2015 19:14:26 +0000 Received: by wiaa2 with SMTP id a2so143311307wia.0 for ; Mon, 30 Mar 2015 12:14:19 -0700 (PDT) X-Received: by 10.194.93.165 with SMTP id cv5mr68636711wjb.24.1427742858966; Mon, 30 Mar 2015 12:14:18 -0700 (PDT) Received: from ards-macbook-pro.local ([90.174.5.130]) by mx.google.com with ESMTPSA id vq9sm17022823wjc.6.2015.03.30.12.14.14 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Mar 2015 12:14:18 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.sourceforge.net, olivier.martin@arm.com, leif.lindholm@linaro.org, roy.franz@linaro.org, ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com, lersek@redhat.com, julien.grall@linaro.org Date: Mon, 30 Mar 2015 21:13:52 +0200 Message-Id: <1427742834-24566-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1427742834-24566-1-git-send-email-ard.biesheuvel@linaro.org> References: <1427742834-24566-1-git-send-email-ard.biesheuvel@linaro.org> X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record X-Headers-End: 1Ycf8j-0003Wt-0r Subject: [edk2] [PATCH v2 1/3] ArmPkg: remove cache maintenance by VA operation range size threshold X-BeenThere: edk2-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list Reply-To: edk2-devel@lists.sourceforge.net List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.sourceforge.net X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This removes the range size threshold for virtual address based cache maintenance instructions that operate on VA ranges to be 'promoted' to use set/way instructions. Doing so is unsafe: set/way operations are fundamentally different from VA operations, and really only suitable for cleaning or invalidating a cache when turning it on or off. To quote the ARM ARM (DDI0487A_d G3.4): """ Since the set/way instructions are performed only locally, there is no guarantee of the atomicity of cache maintenance between different PEs, even if those different PEs are each performing the same cache maintenance instructions at the same time. Since any cacheable line can be allocated into the cache at any time, it is possible for [a] cache line to migrate from an entry in the cache of one PE to the cache of a different PE in a manner that the cache line avoids being affected by set/way based cache maintenance. Therefore, ARM strongly discourages the use of set/way instructions to manage coherency in coherent systems. """ Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/ArmPkg.dec | 3 +-- .../ArmCacheMaintenanceLib.c | 29 ++++++++-------------- .../ArmCacheMaintenanceLib.inf | 3 --- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf | 3 --- ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf | 3 --- ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf | 3 --- ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf | 1 - ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf | 1 - ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf | 1 - ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf | 3 --- ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf | 3 --- ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf | 3 --- ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf | 3 --- ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf | 3 --- ArmPkg/Library/ArmLib/Null/NullArmLib.inf | 3 --- 15 files changed, 12 insertions(+), 53 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 87dbd11b867f..b30de9152c13 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -82,8 +82,7 @@ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002 # This PCD will free the unallocated buffers if their size reach this threshold. # We set the default value to 512MB. - gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043 - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003 + gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index 8501e5c613c7..d8e53df6096e 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -20,27 +20,20 @@ VOID CacheRangeOperation ( IN VOID *Start, IN UINTN Length, - IN CACHE_OPERATION CacheOperation, IN LINE_OPERATION LineOperation ) { UINTN ArmCacheLineLength = ArmDataCacheLineLength(); UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1; - UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold); - if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) { - ArmDrainWriteBuffer (); - CacheOperation (); - } else { - // Align address (rounding down) - UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); - UINTN EndAddress = (UINTN)Start + Length; + // Align address (rounding down) + UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); + UINTN EndAddress = (UINTN)Start + Length; - // Perform the line operation on an address in each cache line - while (AlignedAddress < EndAddress) { - LineOperation(AlignedAddress); - AlignedAddress += ArmCacheLineLength; - } + // Perform the line operation on an address in each cache line + while (AlignedAddress < EndAddress) { + LineOperation(AlignedAddress); + AlignedAddress += ArmCacheLineLength; } } @@ -70,7 +63,7 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA); + CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA); ArmInvalidateInstructionCache (); return Address; } @@ -91,7 +84,7 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA); + CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA); return Address; } @@ -111,7 +104,7 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA); + CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA); return Address; } @@ -122,6 +115,6 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA); + CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA); return Address; } diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf index 5910db09d6ea..d5199729423c 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf @@ -31,6 +31,3 @@ [LibraryClasses] ArmLib BaseLib - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf index e5247848b549..dd585dea91fb 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf @@ -41,6 +41,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf index 3a99e1b713cc..23fbe8673198 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf @@ -43,6 +43,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf index 57ac694cd733..302c09af49dd 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf @@ -38,6 +38,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf index 32d9299629a7..6ac74d985c78 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf @@ -47,5 +47,4 @@ gArmTokenSpaceGuid.PcdRelocateVectorTable [FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold gArmTokenSpaceGuid.PcdCpuVectorBaseAddress diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf index 94dd03d82c5a..239493d3e60d 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf @@ -47,5 +47,4 @@ gArmTokenSpaceGuid.PcdRelocateVectorTable [FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold gArmTokenSpaceGuid.PcdCpuVectorBaseAddress diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf index 69763ed4ff3a..ef3c8f8f72a4 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf @@ -43,5 +43,4 @@ gArmTokenSpaceGuid.PcdRelocateVectorTable [FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold gArmTokenSpaceGuid.PcdCpuVectorBaseAddress diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf index 81661b2391d5..e8aa056fbfea 100644 --- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf +++ b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf @@ -41,6 +41,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf index 0730487cfb9e..556e3dc5ab2a 100644 --- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf +++ b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf @@ -41,6 +41,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf index 55c0ec661a81..01bdfb699656 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf @@ -48,6 +48,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf index bc403d5613ca..ac081068db28 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf @@ -48,6 +48,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf index 4081d1a3e563..a958764f5648 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf @@ -42,6 +42,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf index 21c374f0b293..36860a7bf949 100644 --- a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf +++ b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf @@ -40,6 +40,3 @@ [Protocols] gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold