From patchwork Fri Mar 4 17:02:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 356 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:41:55 -0000 Delivered-To: patches@linaro.org Received: by 10.224.60.68 with SMTP id o4cs21452qah; Fri, 4 Mar 2011 09:02:21 -0800 (PST) Received: by 10.216.172.15 with SMTP id s15mr778721wel.70.1299258141179; Fri, 04 Mar 2011 09:02:21 -0800 (PST) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id f60si3505776wej.119.2011.03.04.09.02.20 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 09:02:21 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) smtp.mail=lee.jones@linaro.org Received: by mail-wy0-f178.google.com with SMTP id 28so2726741wyf.37 for ; Fri, 04 Mar 2011 09:02:20 -0800 (PST) Received: by 10.227.1.151 with SMTP id 23mr741046wbf.175.1299258140767; Fri, 04 Mar 2011 09:02:20 -0800 (PST) Received: from [192.168.0.2] (cpc2-aztw21-0-0-cust264.aztw.cable.virginmedia.com [77.100.97.9]) by mx.google.com with ESMTPS id u9sm1933776wbg.18.2011.03.04.09.02.19 (version=SSLv3 cipher=OTHER); Fri, 04 Mar 2011 09:02:20 -0800 (PST) Message-ID: <4D711B17.8030500@linaro.org> Date: Fri, 04 Mar 2011 17:02:15 +0000 From: Lee Jones User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.14) Gecko/20110223 Lightning/1.0b2 Thunderbird/3.1.8 MIME-Version: 1.0 CC: patches@linaro.org Subject: [PATCHv2 1/2] ARM: perf_event: allow platform-specific interrupt handler Allow a platform-specific IRQ handler to be specified via platform data. This will be used to implement the single-irq workaround for the DB8500. Signed-off-by: Rabin Vincent --- arch/arm/include/asm/pmu.h | 14 ++++++++++++++ arch/arm/kernel/perf_event.c | 17 ++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletions(-) + plat = dev_get_platdata(&pmu_device->dev); + if (plat && plat->handle_irq) + handle_irq = armpmu_platform_irq; + else + handle_irq = armpmu->handle_irq; + if (pmu_device->num_resources < 1) { pr_err("no irqs for PMUs defined\n"); return -ENODEV; @@ -400,7 +415,7 @@ armpmu_reserve_hardware(void) if (irq < 0) continue; - err = request_irq(irq, armpmu->handle_irq, + err = request_irq(irq, handle_irq, IRQF_DISABLED | IRQF_NOBALANCING, "armpmu", NULL); if (err) { diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index 8ccea01..7544ce6 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h @@ -12,11 +12,25 @@ #ifndef __ARM_PMU_H__ #define __ARM_PMU_H__ +#include + enum arm_pmu_type { ARM_PMU_DEVICE_CPU = 0, ARM_NUM_PMU_DEVICES, }; +/* + * struct arm_pmu_platdata - ARM PMU platform data + * + * @handle_irq: an optional handler which will be called from the interrupt and + * passed the address of the low level handler, and can be used to implement + * any platform specific handling before or after calling it. + */ +struct arm_pmu_platdata { + irqreturn_t (*handle_irq)(int irq, void *dev, + irq_handler_t pmu_handler); +}; + #ifdef CONFIG_CPU_HAS_PMU /** diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 5efa264..3239511 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -377,9 +377,18 @@ validate_group(struct perf_event *event) return 0; } +static irqreturn_t armpmu_platform_irq(int irq, void *dev) +{ + struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); + + return plat->handle_irq(irq, dev, armpmu->handle_irq); +} + static int armpmu_reserve_hardware(void) { + struct arm_pmu_platdata *plat; + irq_handler_t handle_irq; int i, err = -ENODEV, irq; pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU); @@ -390,6 +399,12 @@ armpmu_reserve_hardware(void) init_pmu(ARM_PMU_DEVICE_CPU);