From patchwork Thu Mar 29 05:17:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rusty Russell X-Patchwork-Id: 7517 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3A159199202 for ; Thu, 29 Mar 2012 05:18:34 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 03D26A18573 for ; Thu, 29 Mar 2012 05:18:33 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so3405994iag.11 for ; Wed, 28 Mar 2012 22:18:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:in-reply-to:references:user-agent:date:message-id :mime-version:x-gm-message-state:content-type; bh=6uC36EUXpnoSQZ2Ux01Zmh7WZSGsoZRnfn1FHK4JLSk=; b=o6fhbw92q4AmuuAqzyFiXQfV7JALwuEDhamMqfCsYvav4mungiLWD/SVKp1QZsbNz9 AAK/4LzsgcwfXKrmqz+1B8YmSfJPSyU7RRHmVqC9ct+f/qssKgi+J+SwKtbn8QUsbJvC Dq2YjGQleWdH5P7o5adhiBVhQVVZ6VYsaRcpN+fmWVz7Pn32UeAc9eJS1bWnb+atN8tQ Pu5JXUVFj3RuC7mFZOsEYntQr9v0/GTDOSOmHlWbmDVT0xBN1LaitSo9bfYlZpxJXlPt keq3MTpfgftCvwA7ALqjKTg1n9IdmnQ7dYrVw11OvoIMvzgckh78tGEKmrWwLQdAIJ+5 vwzQ== Received: by 10.50.194.226 with SMTP id hz2mr443395igc.44.1332998313780; Wed, 28 Mar 2012 22:18:33 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp21250ibw; Wed, 28 Mar 2012 22:18:32 -0700 (PDT) Received: by 10.68.216.98 with SMTP id op2mr2637908pbc.93.1332998311847; Wed, 28 Mar 2012 22:18:31 -0700 (PDT) Received: from ozlabs.org (ozlabs.org. [203.10.76.45]) by mx.google.com with ESMTPS id t9si6768910pbj.282.2012.03.28.22.18.31 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 28 Mar 2012 22:18:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rusty@ozlabs.org designates 203.10.76.45 as permitted sender) client-ip=203.10.76.45; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rusty@ozlabs.org designates 203.10.76.45 as permitted sender) smtp.mail=rusty@ozlabs.org Received: by ozlabs.org (Postfix, from userid 1011) id 5C615B6FAA; Thu, 29 Mar 2012 16:18:28 +1100 (EST) From: Rusty Russell To: Christoffer Dall , android-virt@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: patches@linaro.org Subject: [PATCH 2/3] ARM: KVM: Fake up performance counters a little more precisely. In-Reply-To: <87y5qkxa88.fsf@rustcorp.com.au> References: <20120312065134.8074.36949.stgit@ubuntu> <87y5qkxa88.fsf@rustcorp.com.au> User-Agent: Notmuch/0.6.1-1 (http://notmuchmail.org) Emacs/23.3.1 (i686-pc-linux-gnu) Date: Thu, 29 Mar 2012 15:47:08 +1030 Message-ID: <87r4wcx9yj.fsf@rustcorp.com.au> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmSu1nvko5PQGM1eTnndwX3HZqOOTmGDxTjM+cNO5M4dv4e1wt3P+VSix4lWbKe/Vbp5uRf Rather than just making all of c9 read-zero/write-discard, this changes it to the explicit profiling registers we need. This is a start for the future implementation were we actually implement performance monitoring, and makes sure we're not discarding important things. Signed-off-by: Rusty Russell --- arch/arm/kvm/emulate.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 65 insertions(+), 2 deletions(-) diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c index aec1b6e..4bdab8f 100644 --- a/arch/arm/kvm/emulate.c +++ b/arch/arm/kvm/emulate.c @@ -238,6 +238,64 @@ static bool read_l2ctlr(struct kvm_vcpu *vcpu, return true; } +static bool read_pmcr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + unsigned long arg) +{ + u32 imp, idcode, num; + + imp = (vcpu->arch.cp15[c0_MIDR] & 0xFF000000) >> 24; + idcode = (vcpu->arch.cp15[c0_MIDR] & 0x00000FF0) >> 4; + /* No counters. */ + num = 0; + + /* Other bits are at reset value. */ + *vcpu_reg(vcpu, p->Rt1) = (imp << 24) | (idcode << 16) | (num << 11); + return true; +} + +/* FIXME: We ignore them enabling performance monitoring. */ +static bool write_pmcr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + unsigned long arg) +{ + u32 val = *vcpu_reg(vcpu, p->Rt1); + + kvm_debug("pmcr write:%s%s%s%s%s%s\n", + val & (1 << 5) ? " DP" : "", + val & (1 << 4) ? " X" : "", + val & (1 << 3) ? " D" : "", + val & (1 << 2) ? " C" : "", + val & (1 << 1) ? " P" : "", + val & (1 << 0) ? " E" : ""); + return true; +} + +static bool read_pmcntenclr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + unsigned long arg) +{ + /* Cycle counter is off, there are no others. */ + *vcpu_reg(vcpu, p->Rt1) = 0; + return true; +} + +static bool write_pmcntenclr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + unsigned long arg) +{ + /* Writing a 1 means disable a counter. That's cool. */ + return true; +} + +static bool write_pmintenclr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + unsigned long arg) +{ + /* Writing a 1 means disable an overflow interrupt. That's cool. */ + return true; +} + static bool access_cp15_reg(struct kvm_vcpu *vcpu, const struct coproc_params *p, unsigned long cp15_reg) @@ -279,13 +337,18 @@ struct coproc_emulate { static const struct coproc_emulate coproc_emulate[] = { /* * L2CTLR access (guest wants to know #CPUs). - * - * FIXME: Hack Alert: Read zero as default case. */ { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, READ, read_l2ctlr}, { CRn( 9), CRm(DF), Op1(DF), Op2(DF), is32, WRITE, ignore_write}, { CRn( 9), CRm(DF), Op1(DF), Op2(DF), is32, READ, read_zero}, + /* Guest reads/writes PMU, assuming there will be one. */ + { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, READ, read_pmcr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, WRITE, write_pmcr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, READ, read_pmcntenclr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, WRITE, write_pmcntenclr}, + { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, WRITE, write_pmintenclr}, + /* * These CRn == 10 entries may not need to exist - if we can * ignore guest attempts to tamper with TLB lockdowns then it