[v2,00/11] ARM v8.1 simd + v8.3 complex insns

Message ID	20171218172425.18200-1-richard.henderson@linaro.org
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:14 -0800 Message-Id: <20171218172425.18200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2 00/11] ARM v8.1 simd + v8.3 complex insns Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	ARM v8.1 simd + v8.3 complex insns \| expand [v2,00/11] ARM v8.1 simd + v8.3 complex insns [v2,01/11] target/arm: Add ARM_FEATURE_V8_1_SIMD [v2,02/11] target/arm: Decode aa64 armv8.1 scalar three same extra [v2,03/11] target/arm: Decode aa64 armv8.1 three same extra [v2,04/11] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element [v2,05/11] target/arm: Decode aa32 armv8.1 three same [v2,06/11] target/arm: Decode aa32 armv8.1 two reg and a scalar [v2,07/11] target/arm: Add ARM_FEATURE_V8_FCMA [v2,08/11] target/arm: Decode aa64 armv8.3 fcadd [v2,09/11] target/arm: Decode aa64 armv8.3 fcmla [v2,10/11] target/arm: Decode aa32 armv8.3 3-same [v2,11/11] target/arm: Decode aa32 armv8.3 2-reg-index

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20171218172425.18200-1-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 18 Dec 2017 09:24:14 -0800
Message-Id: <20171218172425.18200-1-richard.henderson@linaro.org>
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Subject: [Qemu-devel] [PATCH v2 00/11] ARM v8.1 simd + v8.3 complex insns
Precedence: list
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

ARM v8.1 simd + v8.3 complex insns | expand

Message

Richard Henderson Dec. 18, 2017, 5:24 p.m. UTC

I've incorporated Alex's feedback from v1, and have now rebased
upon Alex's work so that the complex insns now support fp16.


r~


Richard Henderson (11):
  target/arm: Add ARM_FEATURE_V8_1_SIMD
  target/arm: Decode aa64 armv8.1 scalar three same extra
  target/arm: Decode aa64 armv8.1 three same extra
  target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
  target/arm: Decode aa32 armv8.1 three same
  target/arm: Decode aa32 armv8.1 two reg and a scalar
  target/arm: Add ARM_FEATURE_V8_FCMA
  target/arm: Decode aa64 armv8.3 fcadd
  target/arm: Decode aa64 armv8.3 fcmla
  target/arm: Decode aa32 armv8.3 3-same
  target/arm: Decode aa32 armv8.3 2-reg-index

 target/arm/cpu.h            |   2 +
 target/arm/helper.h         |  31 ++++
 linux-user/elfload.c        |  10 ++
 target/arm/advsimd_helper.c | 420 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.c            |   2 +
 target/arm/cpu64.c          |   2 +
 target/arm/translate-a64.c  | 382 ++++++++++++++++++++++++++++++++++++----
 target/arm/translate.c      | 239 ++++++++++++++++++++++---
 target/arm/Makefile.objs    |   2 +-
 9 files changed, 1032 insertions(+), 58 deletions(-)
 create mode 100644 target/arm/advsimd_helper.c

-- 
2.14.3