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[v5,0/4] target-arm: add SHA-3, SM3 and SHA512 instruction support

Message ID 20180122172643.29742-1-ard.biesheuvel@linaro.org
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Series target-arm: add SHA-3, SM3 and SHA512 instruction support | expand

Message

Ard Biesheuvel Jan. 22, 2018, 5:26 p.m. UTC 
Changes sinve v4:
- restructure code changes to make it easier on the reviewer
- add Peter's R-b to #4

Changes since v3:
- don't bother with helpers for the SHA3 instructions: they are simple enough
  to be emitted as TCG ops directly
- rebase onto Richard's pending SVE work

Changes since v2:
- fix thinko in big-endian aware handling of 64-bit quantities: this is not
  needed given that the NEON registers are represented as arrays of uint64_t
  so they always appear in the correct order.
- add support for SM3 instructions (Chinese SHA derivative)

Changes since v1:
- update SHA512 patch to adhere more closely to the existing style, and to
  the way the instruction encodings are classified in the ARM ARM (#1)
- add patch implementing the new SHA3 instructions EOR3/RAX1/XAR/BCAX (#2)
- enable support for these instructions in user mode emulation (#3)

Ard Biesheuvel (4):
  target/arm: implement SHA-512 instructions
  target/arm: implement SHA-3 instructions
  target/arm: implement SM3 instructions
  target/arm: enable user-mode SHA-3, SM3 and SHA-512 instruction
    support

 linux-user/elfload.c       |  18 ++
 target/arm/cpu.h           |   3 +
 target/arm/cpu64.c         |   3 +
 target/arm/crypto_helper.c | 192 +++++++++++-
 target/arm/helper.h        |  10 +
 target/arm/translate-a64.c | 319 ++++++++++++++++++++
 6 files changed, 544 insertions(+), 1 deletion(-)

-- 
2.11.0