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[v3,0/5] target/arm: Preparatory work for SVE

Message ID 20180123035349.24538-1-richard.henderson@linaro.org
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Series target/arm: Preparatory work for SVE | expand

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Richard Henderson Jan. 23, 2018, 3:53 a.m. UTC 
Based on PMM's target-arm.next branch, which now has most of v2.

While looking again at ZCR_ELx, I think that there's an existing
bug in the FPCR/FPSR system registers, wherein we do not have an
access function for when the FPU is disabled.


r~


Richard Henderson (5):
  target/arm: Expand vector registers for SVE
  target/arm: Add predicate registers for SVE
  target/arm: Add SVE to migration state
  target/arm: Add ZCR_ELx
  target/arm: Add SVE state to TB->FLAGS

 target/arm/cpu.h           |  84 ++++++++++++++++++------
 target/arm/translate.h     |   2 +
 target/arm/helper.c        | 156 ++++++++++++++++++++++++++++++++++++++++++++-
 target/arm/machine.c       |  88 ++++++++++++++++++++++++-
 target/arm/translate-a64.c |  10 +--
 target/arm/translate.c     |   7 +-
 6 files changed, 318 insertions(+), 29 deletions(-)

-- 
2.14.3

Comments

Peter Maydell Feb. 8, 2018, 2:34 p.m. UTC | #1 
On 23 January 2018 at 03:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Based on PMM's target-arm.next branch, which now has most of v2.

>

> While looking again at ZCR_ELx, I think that there's an existing

> bug in the FPCR/FPSR system registers, wherein we do not have an

> access function for when the FPU is disabled.


Applied to target-arm.next, thanks.

-- PMM