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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:44 -0800 Message-Id: <20180123035349.24538-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 0/5] target/arm: Preparatory work for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Based on PMM's target-arm.next branch, which now has most of v2. While looking again at ZCR_ELx, I think that there's an existing bug in the FPCR/FPSR system registers, wherein we do not have an access function for when the FPU is disabled. r~ Richard Henderson (5): target/arm: Expand vector registers for SVE target/arm: Add predicate registers for SVE target/arm: Add SVE to migration state target/arm: Add ZCR_ELx target/arm: Add SVE state to TB->FLAGS target/arm/cpu.h | 84 ++++++++++++++++++------ target/arm/translate.h | 2 + target/arm/helper.c | 156 ++++++++++++++++++++++++++++++++++++++++++++- target/arm/machine.c | 88 ++++++++++++++++++++++++- target/arm/translate-a64.c | 10 +-- target/arm/translate.c | 7 +- 6 files changed, 318 insertions(+), 29 deletions(-) -- 2.14.3