mbox series

[v5,00/35] target/arm SVE patches

Message ID 20180621015359.12018-1-richard.henderson@linaro.org
Headers show
Series target/arm SVE patches | expand

Message

Richard Henderson June 21, 2018, 1:53 a.m. UTC 
This is the remainder of the SVE enablement patches,
with an extra bonus patch to enable ARMv8.2-DotProd.


r~


Richard Henderson (35):
  target/arm: Implement SVE Memory Contiguous Load Group
  target/arm: Implement SVE Contiguous Load, first-fault and no-fault
  target/arm: Implement SVE Memory Contiguous Store Group
  target/arm: Implement SVE load and broadcast quadword
  target/arm: Implement SVE integer convert to floating-point
  target/arm: Implement SVE floating-point arithmetic (predicated)
  target/arm: Implement SVE FP Multiply-Add Group
  target/arm: Implement SVE Floating Point Accumulating Reduction Group
  target/arm: Implement SVE load and broadcast element
  target/arm: Implement SVE store vector/predicate register
  target/arm: Implement SVE scatter stores
  target/arm: Implement SVE prefetches
  target/arm: Implement SVE gather loads
  target/arm: Implement SVE first-fault gather loads
  target/arm: Implement SVE scatter store vector immediate
  target/arm: Implement SVE floating-point compare vectors
  target/arm: Implement SVE floating-point arithmetic with immediate
  target/arm: Implement SVE Floating Point Multiply Indexed Group
  target/arm: Implement SVE FP Fast Reduction Group
  target/arm: Implement SVE Floating Point Unary Operations-Unpredicated Group
  target/arm: Implement SVE FP Compare with Zero Group
  target/arm: Implement SVE floating-point trig multiply-add coefficient
  target/arm: Implement SVE floating-point convert precision
  target/arm: Implement SVE floating-point convert to integer
  target/arm: Implement SVE floating-point round to integral value
  target/arm: Implement SVE floating-point unary operations
  target/arm: Implement SVE MOVPRFX
  target/arm: Implement SVE floating-point complex add
  target/arm: Implement SVE fp complex multiply add
  target/arm: Pass index to AdvSIMD FCMLA (indexed)
  target/arm: Implement SVE fp complex multiply add (indexed)
  target/arm: Implement SVE dot product (vectors)
  target/arm: Implement SVE dot product (indexed)
  target/arm: Enable SVE for aarch64-linux-user
  target/arm: Implement ARMv8.2-DotProd

 target/arm/cpu.h           |    1 +
 target/arm/helper-sve.h    |  682 ++++++++++++++
 target/arm/helper.h        |   44 +-
 linux-user/elfload.c       |    1 +
 target/arm/cpu.c           |    8 +
 target/arm/cpu64.c         |    2 +
 target/arm/helper.c        |    2 +-
 target/arm/sve_helper.c    | 1827 ++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c |   57 +-
 target/arm/translate-sve.c | 1691 ++++++++++++++++++++++++++++++++-
 target/arm/translate.c     |   81 +-
 target/arm/vec_helper.c    |  283 +++++-
 target/arm/sve.decode      |  422 +++++++++
 13 files changed, 5039 insertions(+), 62 deletions(-)

-- 
2.17.1

Comments

no-reply@patchew.org June 21, 2018, 5:18 a.m. UTC | #1 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180621015359.12018-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v5 00/35] target/arm SVE patches

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20180621015359.12018-1-richard.henderson@linaro.org -> patchew/20180621015359.12018-1-richard.henderson@linaro.org
Switched to a new branch 'test'
20da78ae3f target/arm: Implement ARMv8.2-DotProd
0cb7019b8e target/arm: Enable SVE for aarch64-linux-user
3994a5311f target/arm: Implement SVE dot product (indexed)
68544c457f target/arm: Implement SVE dot product (vectors)
d4de43a8d5 target/arm: Implement SVE fp complex multiply add (indexed)
2c2c7d3891 target/arm: Pass index to AdvSIMD FCMLA (indexed)
a0e69d3f69 target/arm: Implement SVE fp complex multiply add
5f64a686f3 target/arm: Implement SVE floating-point complex add
dad639bc3d target/arm: Implement SVE MOVPRFX
52b01c3388 target/arm: Implement SVE floating-point unary operations
a19d3bf926 target/arm: Implement SVE floating-point round to integral value
3f24de5407 target/arm: Implement SVE floating-point convert to integer
05a1fefa84 target/arm: Implement SVE floating-point convert precision
7162d18555 target/arm: Implement SVE floating-point trig multiply-add coefficient
a0db6af977 target/arm: Implement SVE FP Compare with Zero Group
473295b570 target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group
e4c7547715 target/arm: Implement SVE FP Fast Reduction Group
5c8c7bc112 target/arm: Implement SVE Floating Point Multiply Indexed Group
e25c13b2f2 target/arm: Implement SVE floating-point arithmetic with immediate
bd5f8b5b58 target/arm: Implement SVE floating-point compare vectors
0f3b43fd17 target/arm: Implement SVE scatter store vector immediate
33a026c41d target/arm: Implement SVE first-fault gather loads
91830cd0ff target/arm: Implement SVE gather loads
bd1b3f8926 target/arm: Implement SVE prefetches
e56bc2e4b2 target/arm: Implement SVE scatter stores
0a1f63356b target/arm: Implement SVE store vector/predicate register
c8768a98d4 target/arm: Implement SVE load and broadcast element
2248737380 target/arm: Implement SVE Floating Point Accumulating Reduction Group
eb09ba5657 target/arm: Implement SVE FP Multiply-Add Group
4acac93526 target/arm: Implement SVE floating-point arithmetic (predicated)
690d0c157f target/arm: Implement SVE integer convert to floating-point
cd9ddaedd0 target/arm: Implement SVE load and broadcast quadword
96f8560153 target/arm: Implement SVE Memory Contiguous Store Group
786b7911df target/arm: Implement SVE Contiguous Load, first-fault and no-fault
3a8acf3218 target/arm: Implement SVE Memory Contiguous Load Group

=== OUTPUT BEGIN ===
Checking PATCH 1/35: target/arm: Implement SVE Memory Contiguous Load Group...
ERROR: space prohibited before that close parenthesis ')'
#241: FILE: target/arm/sve_helper.c:2931:
+DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, )

ERROR: space prohibited before that close parenthesis ')'
#242: FILE: target/arm/sve_helper.c:2932:
+DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, )

ERROR: space prohibited before that close parenthesis ')'
#246: FILE: target/arm/sve_helper.c:2936:
+DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, )

ERROR: space prohibited before that close parenthesis ')'
#247: FILE: target/arm/sve_helper.c:2937:
+DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, )

ERROR: space prohibited before that close parenthesis ')'
#249: FILE: target/arm/sve_helper.c:2939:
+DO_LD1(sve_ld1sdu_r, cpu_ldl_data_ra, uint64_t, uint32_t, )

ERROR: space prohibited before that close parenthesis ')'
#250: FILE: target/arm/sve_helper.c:2940:
+DO_LD1(sve_ld1sds_r, cpu_ldl_data_ra, uint64_t, int32_t, )

ERROR: space prohibited before that close parenthesis ')'
#267: FILE: target/arm/sve_helper.c:2957:
+DO_LD1(sve_ld1dd_r, cpu_ldq_data_ra, uint64_t, uint64_t, )

ERROR: space prohibited before that close parenthesis ')'
#268: FILE: target/arm/sve_helper.c:2958:
+DO_LD2(sve_ld2dd_r, cpu_ldq_data_ra, uint64_t, uint64_t, )

ERROR: space prohibited before that close parenthesis ')'
#269: FILE: target/arm/sve_helper.c:2959:
+DO_LD3(sve_ld3dd_r, cpu_ldq_data_ra, uint64_t, uint64_t, )

ERROR: space prohibited before that close parenthesis ')'
#270: FILE: target/arm/sve_helper.c:2960:
+DO_LD4(sve_ld4dd_r, cpu_ldq_data_ra, uint64_t, uint64_t, )

total: 10 errors, 0 warnings, 385 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 2/35: target/arm: Implement SVE Contiguous Load, first-fault and no-fault...
ERROR: space prohibited before that close parenthesis ')'
#204: FILE: target/arm/sve_helper.c:3084:
+DO_LDFF1(bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, )

ERROR: space prohibited before that close parenthesis ')'
#205: FILE: target/arm/sve_helper.c:3085:
+DO_LDFF1(bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, )

ERROR: space prohibited before that close parenthesis ')'
#210: FILE: target/arm/sve_helper.c:3090:
+DO_LDFF1(hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, )

ERROR: space prohibited before that close parenthesis ')'
#211: FILE: target/arm/sve_helper.c:3091:
+DO_LDFF1(hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, )

ERROR: space prohibited before that close parenthesis ')'
#214: FILE: target/arm/sve_helper.c:3094:
+DO_LDFF1(sdu_r, cpu_ldl_data_ra, uint64_t, uint32_t, )

ERROR: space prohibited before that close parenthesis ')'
#215: FILE: target/arm/sve_helper.c:3095:
+DO_LDFF1(sds_r, cpu_ldl_data_ra, uint64_t, int32_t, )

ERROR: space prohibited before that close parenthesis ')'
#217: FILE: target/arm/sve_helper.c:3097:
+DO_LDFF1(dd_r,  cpu_ldq_data_ra, uint64_t, uint64_t, )

total: 7 errors, 0 warnings, 289 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/35: target/arm: Implement SVE Memory Contiguous Store Group...
Checking PATCH 4/35: target/arm: Implement SVE load and broadcast quadword...
Checking PATCH 5/35: target/arm: Implement SVE integer convert to floating-point...
Checking PATCH 6/35: target/arm: Implement SVE floating-point arithmetic (predicated)...
ERROR: spaces required around that '*' (ctx:WxV)
#188: FILE: target/arm/sve_helper.c:2868:
+static inline float16 abd_h(float16 a, float16 b, float_status *s)
                                                                ^

total: 1 errors, 0 warnings, 253 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 7/35: target/arm: Implement SVE FP Multiply-Add Group...
Checking PATCH 8/35: target/arm: Implement SVE Floating Point Accumulating Reduction Group...
Checking PATCH 9/35: target/arm: Implement SVE load and broadcast element...
Checking PATCH 10/35: target/arm: Implement SVE store vector/predicate register...
Checking PATCH 11/35: target/arm: Implement SVE scatter stores...
ERROR: spaces required around that '*' (ctx:WxV)
#137: FILE: target/arm/sve_helper.c:3725:
+    uint32_t *d = vd; TYPEI *m = vm; uint8_t *pg = vg;                  \
                             ^

total: 1 errors, 0 warnings, 246 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 12/35: target/arm: Implement SVE prefetches...
Checking PATCH 13/35: target/arm: Implement SVE gather loads...
Checking PATCH 14/35: target/arm: Implement SVE first-fault gather loads...
ERROR: space prohibited before that close parenthesis ')'
#145: FILE: target/arm/sve_helper.c:3843:
+    DO_LDFF1_ZPZ(NAME, uint64_t, TYPEI, TYPEM, FN, )

total: 1 errors, 0 warnings, 321 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 15/35: target/arm: Implement SVE scatter store vector immediate...
Checking PATCH 16/35: target/arm: Implement SVE floating-point compare vectors...
Checking PATCH 17/35: target/arm: Implement SVE floating-point arithmetic with immediate...
ERROR: spaces required around that '*' (ctx:WxV)
#151: FILE: target/arm/sve_helper.c:3034:
+static inline float16 subr_h(float16 a, float16 b, float_status *s)
                                                                 ^

total: 1 errors, 0 warnings, 250 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 18/35: target/arm: Implement SVE Floating Point Multiply Indexed Group...
ERROR: space prohibited before that close parenthesis ')'
#162: FILE: target/arm/vec_helper.c:519:
+DO_MUL_IDX(gvec_fmul_idx_d, float64, )

ERROR: space prohibited before that close parenthesis ')'
#186: FILE: target/arm/vec_helper.c:543:
+DO_FMLA_IDX(gvec_fmla_idx_d, float64, )

total: 2 errors, 0 warnings, 158 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 19/35: target/arm: Implement SVE FP Fast Reduction Group...
ERROR: spaces required around that '*' (ctx:WxV)
#91: FILE: target/arm/sve_helper.c:2864:
+static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
                                                    ^

total: 1 errors, 0 warnings, 185 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 20/35: target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group...
ERROR: spaces required around that '*' (ctx:WxV)
#56: FILE: target/arm/translate-sve.c:3514:
+static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
                                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#56: FILE: target/arm/translate-sve.c:3514:
+static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
                                                                            ^

total: 2 errors, 0 warnings, 104 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 21/35: target/arm: Implement SVE FP Compare with Zero Group...
ERROR: Macros with complex values should be enclosed in parenthesis
#98: FILE: target/arm/sve_helper.c:3365:
+#define DO_FCMLE(TYPE, X, Y, ST)  TYPE##_compare(X, Y, ST) <= 0

ERROR: Macros with complex values should be enclosed in parenthesis
#99: FILE: target/arm/sve_helper.c:3366:
+#define DO_FCMLT(TYPE, X, Y, ST)  TYPE##_compare(X, Y, ST) < 0

total: 2 errors, 0 warnings, 174 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 22/35: target/arm: Implement SVE floating-point trig multiply-add coefficient...
Checking PATCH 23/35: target/arm: Implement SVE floating-point convert precision...
Checking PATCH 24/35: target/arm: Implement SVE floating-point convert to integer...
Checking PATCH 25/35: target/arm: Implement SVE floating-point round to integral value...
Checking PATCH 26/35: target/arm: Implement SVE floating-point unary operations...
Checking PATCH 27/35: target/arm: Implement SVE MOVPRFX...
Checking PATCH 28/35: target/arm: Implement SVE floating-point complex add...
Checking PATCH 29/35: target/arm: Implement SVE fp complex multiply add...
Checking PATCH 30/35: target/arm: Pass index to AdvSIMD FCMLA (indexed)...
Checking PATCH 31/35: target/arm: Implement SVE fp complex multiply add (indexed)...
Checking PATCH 32/35: target/arm: Implement SVE dot product (vectors)...
Checking PATCH 33/35: target/arm: Implement SVE dot product (indexed)...
Checking PATCH 34/35: target/arm: Enable SVE for aarch64-linux-user...
Checking PATCH 35/35: target/arm: Implement ARMv8.2-DotProd...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Alex Bennée June 26, 2018, 9:41 a.m. UTC | #2 
Richard Henderson <richard.henderson@linaro.org> writes:

> This is the remainder of the SVE enablement patches,

> with an extra bonus patch to enable ARMv8.2-DotProd.


Have a:

Tested-by: Alex Bennée <alex.bennee@linaro.org>


Passes the whole sve-all-short test set with this series applied.

>

>

> r~

>

>

> Richard Henderson (35):

>   target/arm: Implement SVE Memory Contiguous Load Group

>   target/arm: Implement SVE Contiguous Load, first-fault and no-fault

>   target/arm: Implement SVE Memory Contiguous Store Group

>   target/arm: Implement SVE load and broadcast quadword

>   target/arm: Implement SVE integer convert to floating-point

>   target/arm: Implement SVE floating-point arithmetic (predicated)

>   target/arm: Implement SVE FP Multiply-Add Group

>   target/arm: Implement SVE Floating Point Accumulating Reduction Group

>   target/arm: Implement SVE load and broadcast element

>   target/arm: Implement SVE store vector/predicate register

>   target/arm: Implement SVE scatter stores

>   target/arm: Implement SVE prefetches

>   target/arm: Implement SVE gather loads

>   target/arm: Implement SVE first-fault gather loads

>   target/arm: Implement SVE scatter store vector immediate

>   target/arm: Implement SVE floating-point compare vectors

>   target/arm: Implement SVE floating-point arithmetic with immediate

>   target/arm: Implement SVE Floating Point Multiply Indexed Group

>   target/arm: Implement SVE FP Fast Reduction Group

>   target/arm: Implement SVE Floating Point Unary Operations-Unpredicated Group

>   target/arm: Implement SVE FP Compare with Zero Group

>   target/arm: Implement SVE floating-point trig multiply-add coefficient

>   target/arm: Implement SVE floating-point convert precision

>   target/arm: Implement SVE floating-point convert to integer

>   target/arm: Implement SVE floating-point round to integral value

>   target/arm: Implement SVE floating-point unary operations

>   target/arm: Implement SVE MOVPRFX

>   target/arm: Implement SVE floating-point complex add

>   target/arm: Implement SVE fp complex multiply add

>   target/arm: Pass index to AdvSIMD FCMLA (indexed)

>   target/arm: Implement SVE fp complex multiply add (indexed)

>   target/arm: Implement SVE dot product (vectors)

>   target/arm: Implement SVE dot product (indexed)

>   target/arm: Enable SVE for aarch64-linux-user

>   target/arm: Implement ARMv8.2-DotProd

>

>  target/arm/cpu.h           |    1 +

>  target/arm/helper-sve.h    |  682 ++++++++++++++

>  target/arm/helper.h        |   44 +-

>  linux-user/elfload.c       |    1 +

>  target/arm/cpu.c           |    8 +

>  target/arm/cpu64.c         |    2 +

>  target/arm/helper.c        |    2 +-

>  target/arm/sve_helper.c    | 1827 ++++++++++++++++++++++++++++++++++++

>  target/arm/translate-a64.c |   57 +-

>  target/arm/translate-sve.c | 1691 ++++++++++++++++++++++++++++++++-

>  target/arm/translate.c     |   81 +-

>  target/arm/vec_helper.c    |  283 +++++-

>  target/arm/sve.decode      |  422 +++++++++

>  13 files changed, 5039 insertions(+), 62 deletions(-)



--
Alex Bennée