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[0/6] target/arm SVE updates

Message ID 20180629001538.11415-1-richard.henderson@linaro.org
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Series target/arm SVE updates | expand

Message

Richard Henderson June 29, 2018, 12:15 a.m. UTC 
Patch 1 fixes the SIGFPE that Alex found with --test-sve=3.
Patch 2 fixes a problem pointed out by Laurent, presumably
via inspection.
  
The rest begin enabling cpu features for -cpu max.
I'm still working on SVE itself, but these are standalone
and perhaps worth merging before softfreeze. 
  
 
r~
 

Richard Henderson (6):
  target/arm: Fix SVE signed division vs x86 overflow exception
  target/arm: Fix SVE system register access checks
  target/arm: Prune a57 features from max
  target/arm: Prune a15 features from max
  target/arm: Add ID_ISAR6
  target/arm: Set ISAR bits for -cpu max

 target/arm/cpu.h           |  1 +
 target/arm/cpu.c           | 31 +++++++++++++++++--------
 target/arm/cpu64.c         | 47 ++++++++++++++++++++++++--------------
 target/arm/helper.c        | 13 +++++------
 target/arm/sve_helper.c    | 16 +++++++++----
 target/arm/translate-a64.c |  5 ++--
 6 files changed, 71 insertions(+), 42 deletions(-)

-- 
2.17.1

Comments

Philippe Mathieu-Daudé June 29, 2018, 1:06 a.m. UTC | #1 
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> Patch 1 fixes the SIGFPE that Alex found with --test-sve=3.

> Patch 2 fixes a problem pointed out by Laurent, presumably

> via inspection.

>   

> The rest begin enabling cpu features for -cpu max.

> I'm still working on SVE itself, but these are standalone

> and perhaps worth merging before softfreeze.


I realized once reviewed the last patch, that this series is
Based-on: 20180627043328.11531-1-richard.henderson@linaro.org
http://lists.nongnu.org/archive/html/qemu-devel/2018-06/msg07698.html

Also probably meaning no-reply@patchew.org is laggy/dead.

> Richard Henderson (6):

>   target/arm: Fix SVE signed division vs x86 overflow exception

>   target/arm: Fix SVE system register access checks

>   target/arm: Prune a57 features from max

>   target/arm: Prune a15 features from max

>   target/arm: Add ID_ISAR6

>   target/arm: Set ISAR bits for -cpu max

> 

>  target/arm/cpu.h           |  1 +

>  target/arm/cpu.c           | 31 +++++++++++++++++--------

>  target/arm/cpu64.c         | 47 ++++++++++++++++++++++++--------------

>  target/arm/helper.c        | 13 +++++------

>  target/arm/sve_helper.c    | 16 +++++++++----

>  target/arm/translate-a64.c |  5 ++--

>  6 files changed, 71 insertions(+), 42 deletions(-)

>