Message ID | 20201012095804.3335117-1-f4bug@amsat.org |
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Headers | show
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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id x15sm27187433wrr.36.2020.10.12.02.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 02:58:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PATCH v4 00/21] hw/mips: Set CPU frequency Date: Mon, 12 Oct 2020 11:57:43 +0200 Message-Id: <20201012095804.3335117-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. 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Series |
hw/mips: Set CPU frequency
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expand
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On 10/12/20 11:57 AM, Philippe Mathieu-Daudé wrote: > Since v3: > - Introduced mips_cpu_create_with_clock() helper (Huacai) > - Added R-b tags > > Since v2: > - Renamed "clk" -> "clk-in" > - Renamed "cpuclk-out -> "cpu-refclk" > > Missing review: patches 7, 10-13, 15-21 > > ~~~ > > All the MIPS cores emulated by QEMU provides the Coproc#0 > 'Count' register which can be used as a free running timer. > > Since it's introduction in 2005 this timer uses a fixed > frequency of 100 MHz (for a CPU freq of 200 MHz). > While this is not an issue with Linux guests, it makes > some firmwares behave incorrectly. > > The Clock API allow propagating clocks. It is particularly > useful when hardware dynamicly changes clock frequencies. > > To be able to model such MIPS hardware, we need to refactor > the MIPS hardware code to handle clocks. Thanks, series applied to mips-next.