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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id x15sm27187433wrr.36.2020.10.12.02.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 02:58:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v4 00/21] hw/mips: Set CPU frequency Date: Mon, 12 Oct 2020 11:57:43 +0200 Message-Id: <20201012095804.3335117-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Luc Michel , Eduardo Habkost , Paul Burton , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?b?w6k=?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Since v3: - Introduced mips_cpu_create_with_clock() helper (Huacai) - Added R-b tags Since v2: - Renamed "clk" -> "clk-in" - Renamed "cpuclk-out -> "cpu-refclk" Missing review: patches 7, 10-13, 15-21 ~~~ All the MIPS cores emulated by QEMU provides the Coproc#0 'Count' register which can be used as a free running timer. Since it's introduction in 2005 this timer uses a fixed frequency of 100 MHz (for a CPU freq of 200 MHz). While this is not an issue with Linux guests, it makes some firmwares behave incorrectly. The Clock API allow propagating clocks. It is particularly useful when hardware dynamicly changes clock frequencies. To be able to model such MIPS hardware, we need to refactor the MIPS hardware code to handle clocks. This series is organized as follow: 1/ qdev/clock patches already reviewed but not merged 2/ refactor the CP0 timer period to allow dynamic changes 3/ MIPS CPU get an optional input clock 4/ set correct CPU frequencies to all boards I used a MIPSsim test suggested by Thomas. The test is available on the list: https://mid.mail-archive.com/20200928171539.788309-17-f4bug@amsat.org Possible follow up: - QOM'ify the GIC - let the GIC handle dynamic clock changes Regards, Phil. Luc Michel (1): hw/core/clock: add the clock_new helper function Philippe Mathieu-Daudé (20): util/cutils: Introduce freq_to_str() to display Hertz units qdev-monitor: Display frequencies scaled to SI unit hw/qdev-clock: Display error hint when clock is missing from device target/mips: Move cpu_mips_get_random() with CP0 helpers target/mips/cp0_timer: Explicit unit in variable name target/mips/cp0_timer: Document TIMER_PERIOD origin target/mips: Move cp0_count_ns to CPUMIPSState target/mips/cpu: Calculate the CP0 timer period using the CPU frequency target/mips/cpu: Make cp0_count_rate a property target/mips/cpu: Allow the CPU to use dynamic frequencies target/mips/cpu: Introduce mips_cpu_create_with_clock() helper hw/mips/r4k: Explicit CPU frequency is 200 MHz hw/mips/fuloong2e: Set CPU frequency to 533 MHz hw/mips/mipssim: Correct CPU frequency hw/mips/jazz: Correct CPU frequencies hw/mips/cps: Expose input clock and connect it to CPU cores hw/mips/boston: Set CPU frequency to 1 GHz hw/mips/malta: Set CPU frequency to 320 MHz hw/mips/cps: Do not allow use without input clock target/mips/cpu: Display warning when CPU is used without input clock include/hw/clock.h | 13 ++++++++++ include/hw/mips/cps.h | 2 ++ include/qemu/cutils.h | 12 +++++++++ target/mips/cpu.h | 26 +++++++++++++++++++ target/mips/internal.h | 2 +- hw/core/clock.c | 15 +++++++++++ hw/core/qdev-clock.c | 11 ++++++++ hw/mips/boston.c | 13 ++++++++++ hw/mips/cps.c | 9 +++++++ hw/mips/fuloong2e.c | 7 +++++- hw/mips/jazz.c | 15 ++++++++++- hw/mips/malta.c | 19 +++++++++++--- hw/mips/mipssim.c | 11 +++++++- hw/mips/r4k.c | 7 +++++- qdev-monitor.c | 8 +++--- target/mips/cp0_helper.c | 25 +++++++++++++++++++ target/mips/cp0_timer.c | 51 ++++++++++--------------------------- target/mips/cpu.c | 54 +++++++++++++++++++++++++++++++++++++++- util/cutils.c | 14 +++++++++++ 19 files changed, 264 insertions(+), 50 deletions(-) -- 2.26.2