mbox series

[PULL,00/44] mips-next patches for 2020-10-17

Message ID 20201017140243.1078718-1-f4bug@amsat.org
Headers show
Series mips-next patches for 2020-10-17 | expand

Message

Philippe Mathieu-Daudé Oct. 17, 2020, 2:01 p.m. UTC 
The following changes since commit 7daf8f8d011cdd5d3e86930ed2bde969425c790c:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging=
 (2020-10-16 17:39:01 +0100)

are available in the Git repository at:

  https://gitlab.com/philmd/qemu.git tags/mips-next-20201017

for you to fetch changes up to 68fa519a6cb455005317bd61f95214b58b2f1e69:

  target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) (20=
20-10-17 13:59:40 +0200)

----------------------------------------------------------------
MIPS patches queue

. Fix some comment spelling errors
. Demacro some TCG helpers
. Add loongson-ext lswc2/lsdc2 group of instructions
. Log unimplemented cache opcode
. Increase number of TLB entries on the 34Kf core
. Allow the CPU to use dynamic frequencies
. Calculate the CP0 timer period using the CPU frequency
. Set CPU frequency for each machine
. Fix Malta FPGA I/O region size
. Allow running qtests when ROM is missing
. Add record/replay acceptance tests
. Update MIPS CPU documentation
. MAINTAINERS updates

CI jobs results:
  https://gitlab.com/philmd/qemu/-/pipelines/203931842
  https://travis-ci.org/github/philmd/qemu/builds/736491461
  https://cirrus-ci.com/build/6272264062631936
  https://app.shippable.com/github/philmd/qemu/runs/886/summary/console
----------------------------------------------------------------

Aleksandar Markovic (4):
  target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>
  target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>
  target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>
  MAINTAINERS: Remove myself

Eduardo Habkost (1):
  hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON

Huacai Chen (1):
  docs/system: Update MIPS CPU documentation

Jiaxun Yang (3):
  target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
  target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
  target/mips: Add loongson-ext lsdc2 group of instructions

Luc Michel (1):
  hw/core/clock: Add the clock_new helper function

Pavel Dovgalyuk (2):
  hw/mips: Remove exit(1) in case of missing ROM
  tests/acceptance: Add MIPS record/replay tests

Philippe Mathieu-Daud=C3=A9 (31):
  util/cutils: Introduce freq_to_str() to display Hertz units
  hw/qdev-clock: Display error hint when clock is missing from device
  target/mips/op_helper: Convert multiple if() to switch case
  target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op
  target/mips/op_helper: Log unimplemented cache opcode
  target/mips: Move cpu_mips_get_random() with CP0 helpers
  target/mips/cp0_timer: Explicit unit in variable name
  target/mips/cp0_timer: Document TIMER_PERIOD origin
  target/mips: Move cp0_count_ns to CPUMIPSState
  target/mips/cpu: Calculate the CP0 timer period using the CPU
    frequency
  target/mips/cpu: Make cp0_count_rate a property
  target/mips/cpu: Allow the CPU to use dynamic frequencies
  target/mips/cpu: Introduce mips_cpu_create_with_clock() helper
  hw/mips/r4k: Explicit CPU frequency is 200 MHz
  hw/mips/fuloong2e: Set CPU frequency to 533 MHz
  hw/mips/mipssim: Correct CPU frequency
  hw/mips/jazz: Correct CPU frequencies
  hw/mips/cps: Expose input clock and connect it to CPU cores
  hw/mips/boston: Set CPU frequency to 1 GHz
  hw/mips/malta: Set CPU frequency to 320 MHz
  hw/mips/cps: Do not allow use without input clock
  target/mips/cpu: Display warning when CPU is used without input clock
  hw/mips/malta: Fix FPGA I/O region size
  hw/mips/malta: Move gt64120 related code together
  hw/mips/malta: Use clearer qdev style
  hw/mips: Simplify loading 64-bit ELF kernels
  hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
  MAINTAINERS: Put myself forward for MIPS target
  MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton
    mail
  MAINTAINERS: Remove duplicated Malta test entries
  target/mips: Increase number of TLB entries on the 34Kf core (16 ->
    64)

zhaolichang (1):
  target/mips: Fix some comment spelling errors

 docs/system/cpu-models-mips.rst.inc |  10 +-
 include/hw/clock.h                  |  13 +
 include/hw/mips/cps.h               |   2 +
 include/hw/mips/mips.h              |   4 +-
 include/qemu/cutils.h               |  12 +
 target/mips/cpu.h                   |  26 ++
 target/mips/internal.h              |   4 +-
 hw/core/clock.c                     |  15 +
 hw/core/qdev-clock.c                |  11 +
 hw/mips/boston.c                    |  21 +-
 hw/mips/cps.c                       |   9 +
 hw/mips/fuloong2e.c                 |  18 +-
 hw/mips/jazz.c                      |  23 +-
 hw/mips/malta.c                     |  59 ++--
 hw/mips/mipssim.c                   |  30 +-
 hw/mips/r4k.c                       |  16 +-
 target/mips/cp0_helper.c            |  25 ++
 target/mips/cp0_timer.c             |  51 +---
 target/mips/cpu.c                   |  55 +++-
 target/mips/fpu_helper.c            | 220 ++++++++++----
 target/mips/op_helper.c             |  27 +-
 target/mips/translate.c             | 453 +++++++++++++++++++++++++++-
 util/cutils.c                       |  14 +
 MAINTAINERS                         |  25 +-
 target/mips/translate_init.c.inc    |   4 +-
 tests/acceptance/replay_kernel.py   | 167 +++++++++-
 26 files changed, 1119 insertions(+), 195 deletions(-)

--=20
2.26.2

Comments

Peter Maydell Oct. 19, 2020, 10:45 a.m. UTC | #1 
On Sat, 17 Oct 2020 at 15:05, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>

> The following changes since commit 7daf8f8d011cdd5d3e86930ed2bde969425c790c:

>

>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging=

>  (2020-10-16 17:39:01 +0100)

>

> are available in the Git repository at:

>

>   https://gitlab.com/philmd/qemu.git tags/mips-next-20201017

>

> for you to fetch changes up to 68fa519a6cb455005317bd61f95214b58b2f1e69:

>

>   target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) (20=

> 20-10-17 13:59:40 +0200)

>

> ----------------------------------------------------------------

> MIPS patches queue

>

> . Fix some comment spelling errors

> . Demacro some TCG helpers

> . Add loongson-ext lswc2/lsdc2 group of instructions

> . Log unimplemented cache opcode

> . Increase number of TLB entries on the 34Kf core

> . Allow the CPU to use dynamic frequencies

> . Calculate the CP0 timer period using the CPU frequency

> . Set CPU frequency for each machine

> . Fix Malta FPGA I/O region size

> . Allow running qtests when ROM is missing

> . Add record/replay acceptance tests

> . Update MIPS CPU documentation

> . MAINTAINERS updates

>

> CI jobs results:

>   https://gitlab.com/philmd/qemu/-/pipelines/203931842

>   https://travis-ci.org/github/philmd/qemu/builds/736491461

>   https://cirrus-ci.com/build/6272264062631936

>   https://app.shippable.com/github/philmd/qemu/runs/886/summary/console

> ----------------------------------------------------------------



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM