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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:04:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 00/20] accel/tcg: Introduce tlb_fill_align hook Date: Tue, 8 Oct 2024 17:04:33 -0700 Message-ID: <20241009000453.315652-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This new hook will allow targets to recognize an alignment fault with the correct priority with respect to other faults that can be raised by paging. This should fix several hppa fault priority issues, most importantly that access permissions come before alignment. This should fix the documented error in the Arm alignment fault due to memory type. Changes for v3: - Change the tlb_fill_hook to return data into provided CPUTLBEntryFull, instead of calling tlb_set_page*. - I have dropped some r-b, correspondingly. Patches needing review: 05-accel-tcg-Add-TCGCPUOps.tlb_fill_align.patch 06-accel-tcg-Use-the-alignment-test-in-tlb_fill_alig.patch 11-target-hppa-Implement-TCGCPUOps.tlb_fill_align.patch 19-target-arm-Implement-TCGCPUOps.tlb_fill_align.patch r~ Richard Henderson (20): accel/tcg: Assert noreturn from write-only page for atomics include/exec/memop: Move get_alignment_bits from tcg.h include/exec/memop: Rename get_alignment_bits include/exec/memop: Introduce memop_atomicity_bits accel/tcg: Add TCGCPUOps.tlb_fill_align accel/tcg: Use the alignment test in tlb_fill_align target/hppa: Add MemOp argument to hppa_get_physical_address target/hppa: Perform access rights before protection id check target/hppa: Fix priority of T, D, and B page faults target/hppa: Handle alignment faults in hppa_get_physical_address target/hppa: Implement TCGCPUOps.tlb_fill_align target/arm: Pass MemOp to get_phys_addr target/arm: Pass MemOp to get_phys_addr_with_space_nogpc target/arm: Pass MemOp to get_phys_addr_gpc target/arm: Pass MemOp to get_phys_addr_nogpc target/arm: Pass MemOp through get_phys_addr_twostage target/arm: Pass MemOp to get_phys_addr_lpae target/arm: Move device detection earlier in get_phys_addr_lpae target/arm: Implement TCGCPUOps.tlb_fill_align target/arm: Fix alignment fault priority in get_phys_addr_lpae include/exec/memop.h | 47 ++++++++++ include/hw/core/cpu.h | 4 +- include/hw/core/tcg-cpu-ops.h | 26 ++++++ include/qemu/typedefs.h | 1 + include/tcg/tcg.h | 23 ----- target/arm/internals.h | 12 +-- target/hppa/cpu.h | 8 +- accel/tcg/cputlb.c | 160 +++++++++++++++++---------------- accel/tcg/user-exec.c | 4 +- target/arm/cpu.c | 2 +- target/arm/helper.c | 9 +- target/arm/ptw.c | 141 ++++++++++++++++------------- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/m_helper.c | 8 +- target/arm/tcg/tlb_helper.c | 49 ++++------ target/arm/tcg/translate-a64.c | 4 +- target/hppa/cpu.c | 2 +- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 55 +++++++----- target/hppa/op_helper.c | 2 +- target/xtensa/translate.c | 2 +- tcg/tcg-op-ldst.c | 6 +- tcg/tcg.c | 2 +- tcg/arm/tcg-target.c.inc | 4 +- tcg/sparc64/tcg-target.c.inc | 2 +- 25 files changed, 326 insertions(+), 251 deletions(-)