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[00/61] target/arm: Implement FEAT_SME2

Message ID 20250206195715.2150758-1-richard.henderson@linaro.org
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Series target/arm: Implement FEAT_SME2 | expand

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Richard Henderson Feb. 6, 2025, 7:56 p.m. UTC 
Based-on: 20250201164012.1660228-1-peter.maydell@linaro.org
("[PATCH v2 00/69] target/arm: FEAT_AFP and FEAT_RPRES")

This implements the Scalar Matrix Extensions, version 2, plus two
trivial extensions for float16 and bfloat16.

This hasn't been tested much at all; I need to either get FVP up and
running for RISU comparison, or write some stand-alone test cases.
But in the meantime this could use some eyes.

SME2 is the first vector-like extension we've had that has dynamic
indexing of registers: ZArray[(rv + offset) % svl], where RV is a
general register.  So the first thing I do is extend TCG's gvec
support to handle TCGv_ptr base + offset addressing.  I only changed
enough to handle what I needed within SME2; changing it all would be
a big job, and it would (at least for the moment) remain unused.

Still to-do are few more extensions for SME2p1.


r~


Richard Henderson (61):
  tcg: Add dbase argument to do_dup_store
  tcg: Add dbase argument to do_dup
  tcg: Add dbase argument to expand_clr
  tcg: Add base arguments to check_overlap_[234]
  tcg: Split out tcg_gen_gvec_2_var
  tcg: Split out tcg_gen_gvec_3_var
  tcg: Split out tcg_gen_gvec_mov_var
  tcg: Split out tcg_gen_gvec_{add,sub}_var
  target/arm: Introduce FPST_ZA, FPST_ZA_F16
  target/arm: Use FPST_ZA for sme_fmopa_[hsd]
  target/arm: Rename zarray to za_state.za
  target/arm: Add isar_feature_aa64_sme2*
  target/arm: Add ZT0
  target/arm: Add zt0_excp_el to DisasContext
  target/arm: Implement SME2 ZERO ZT0
  target/arm: Implement SME2 LDR/STR ZT0
  target/arm: Implement SME2 MOVT
  target/arm: Split get_tile_rowcol argument tile_index
  target/arm: Rename MOVA for translate
  target/arm: Implement SME2 MOVA to/from tile, multiple registers
  target/arm: Split out get_zarray
  target/arm: Implement SME2 MOVA to/from array, multiple registers
  target/arm: Implement SME2 BMOPA
  target/arm: Implement SME2 SMOPS, UMOPS (2-way)
  target/arm: Introduce gen_gvec_sve2_sqdmulh
  target/arm: Implement SME2 Multiple and Single SVE Destructive
  target/arm: Implement SME2 Multiple Vectors SVE Destructive
  target/arm: Implement SME2 ADD/SUB (array results, multiple and single
    vector)
  target/arm: Implement SME2 ADD/SUB (array results, multiple vectors)
  target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s
  target/arm: Implement SME2 FMLAL, BFMLAL
  target/arm: Implement SME2 FDOT
  target/arm: Implement SME2 BFDOT
  target/arm: Implement SME2 FVDOT, BFVDOT
  target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh]
  target/arm: Remove helper_gvec_sudot_idx_4b
  target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT
  target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT
  target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL
  target/arm: Implement SME2 SMLALL, SMLSLL, UMLALL, UMLSLL
  target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix
  target/arm: Implement SME2 FMLA, FMLS
  target/arm: Implement SME2 BFMLA, BFMLS
  target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB
  target/arm: Remove CPUARMState.vfp.scratch
  target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN
  target/arm: Implement SME2 FCVT (widening), FCVTL
  target/arm: Implement SME2 FCVTZS, FCVTZU
  target/arm: Implement SME2 SCVTF, UCVTF
  target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA
  target/arm: Introduce do_[us]sat_[bhs] macros
  target/arm: Use do_[us]sat_[bhs] in sve_helper.c
  target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU
  target/arm: Implement SME2 SUNPK, UUNPK
  target/arm: Implement SME2 ZIP, UZP (four registers)
  target/arm: Move do_urshr, do_srshr to vec_internal.h
  target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN
  target/arm: Implement SME2 ZIP, UZP (two registers)
  target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP
  target/arm: Implement SME2 SEL
  target/arm: Enable FEAT_SME2, FEAT_SME_F16F16, FEAT_SVE_B16B16 on -cpu
    max

 include/tcg/tcg-op-gvec-common.h |   20 +
 target/arm/cpu-features.h        |   35 +
 target/arm/cpu.h                 |   68 +-
 target/arm/helper.h              |   47 +-
 target/arm/syndrome.h            |    1 +
 target/arm/tcg/helper-sme.h      |  164 ++++
 target/arm/tcg/translate-a64.h   |    4 +
 target/arm/tcg/translate.h       |   11 +
 target/arm/tcg/vec_internal.h    |   32 +
 linux-user/aarch64/signal.c      |    4 +-
 target/arm/cpu.c                 |   11 +-
 target/arm/helper.c              |    2 +-
 target/arm/machine.c             |   23 +-
 target/arm/tcg/cpu64.c           |    7 +-
 target/arm/tcg/gengvec.c         |    6 +
 target/arm/tcg/gengvec64.c       |   11 +
 target/arm/tcg/helper-a64.c      |    2 +
 target/arm/tcg/hflags.c          |   34 +-
 target/arm/tcg/mve_helper.c      |   21 -
 target/arm/tcg/sme_helper.c      |  867 +++++++++++++++++++--
 target/arm/tcg/sve_helper.c      |  137 ++--
 target/arm/tcg/translate-a64.c   |   15 +-
 target/arm/tcg/translate-neon.c  |   18 +-
 target/arm/tcg/translate-sme.c   | 1238 +++++++++++++++++++++++++++++-
 target/arm/tcg/translate-sve.c   |   28 +-
 target/arm/tcg/vec_helper.c      |  162 +++-
 target/arm/vfp_helper.c          |   10 +
 tcg/tcg-op-gvec.c                |  363 +++++----
 docs/system/arm/emulation.rst    |    3 +
 target/arm/tcg/sme.decode        |  823 +++++++++++++++++++-
 30 files changed, 3719 insertions(+), 448 deletions(-)