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[0/7] target/riscv: Fix write_misa vs aligned next_pc

Message ID 20250425152311.804338-1-richard.henderson@linaro.org
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Series target/riscv: Fix write_misa vs aligned next_pc | expand

Message

Richard Henderson April 25, 2025, 3:23 p.m. UTC 
As discussed, the use of GETPC() within write_misa is wrong.
I've done just enough plumbing to get the helper return address
piped down to write_misa, so that we can make use of unwind data.

AFAIK, nothing in check-tcg or check-functional would test this.
It shouldn't be too hard to write a test akin to issue1060.S,
but I'm going to leave that to someone else.


r~


Richard Henderson (7):
  target/riscv: Pass ra to riscv_csr_write_fn
  target/riscv: Pass ra to riscv_csrrw_do64
  target/riscv: Pass ra to riscv_csrrw_do128
  target/riscv: Pass ra to riscv_csrrw
  target/riscv: Pass ra to riscv_csrrw_i128
  target/riscv: Move insn_len to internals.h
  target/riscv: Fix write_misa vs aligned next_pc

 target/riscv/cpu.h       |  15 ++-
 target/riscv/internals.h |   5 +
 hw/riscv/riscv_hart.c    |   2 +-
 target/riscv/csr.c       | 278 +++++++++++++++++++++------------------
 target/riscv/op_helper.c |  13 +-
 target/riscv/translate.c |   5 -
 6 files changed, 169 insertions(+), 149 deletions(-)

Comments

Daniel Henrique Barboza April 26, 2025, 8:25 a.m. UTC | #1 
On 4/25/25 12:23 PM, Richard Henderson wrote:
> As discussed, the use of GETPC() within write_misa is wrong.
> I've done just enough plumbing to get the helper return address
> piped down to write_misa, so that we can make use of unwind data.
> 
> AFAIK, nothing in check-tcg or check-functional would test this.
> It shouldn't be too hard to write a test akin to issue1060.S,
> but I'm going to leave that to someone else.

All patches:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

> 
> 
> r~
> 
> 
> Richard Henderson (7):
>    target/riscv: Pass ra to riscv_csr_write_fn
>    target/riscv: Pass ra to riscv_csrrw_do64
>    target/riscv: Pass ra to riscv_csrrw_do128
>    target/riscv: Pass ra to riscv_csrrw
>    target/riscv: Pass ra to riscv_csrrw_i128
>    target/riscv: Move insn_len to internals.h
>    target/riscv: Fix write_misa vs aligned next_pc
> 
>   target/riscv/cpu.h       |  15 ++-
>   target/riscv/internals.h |   5 +
>   hw/riscv/riscv_hart.c    |   2 +-
>   target/riscv/csr.c       | 278 +++++++++++++++++++++------------------
>   target/riscv/op_helper.c |  13 +-
>   target/riscv/translate.c |   5 -
>   6 files changed, 169 insertions(+), 149 deletions(-)
>