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[0/2] target/arm: Implement ID_AA64PFR2_EL1

Message ID 20250609104146.1547437-1-peter.maydell@linaro.org
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Series target/arm: Implement ID_AA64PFR2_EL1 | expand

Message

Peter Maydell June 9, 2025, 10:41 a.m. UTC 
The ID register ID_AA64PFR2_EL1 is in the space previously reserved
in the system register ID space, but recent versions of the
architecture have started to define fields in it to advertise the
presence of new architectural features. We don't implement any
of those new features yet, but will need to do so at some point.
(Notably, the GICv5 beta spec defines a field in this register
to advertise the GICv5 CPU interface.)

This patchset gives ID_AA64PFR2_EL1 a backing field in the CPU
ID regs struct, defines the field names, and reads it from KVM if
it's present there. The only visible behaviour change is the
name we present to the user via the gdbstub.

Commit 1 is a code movement one to clear some more stuff out
of cpu.h that doesn't need to be there; it's mostly because of that
that I'm sending this patchset rather than holding on to it until
I have some GICv5 patches ready to send.

(Compare commit f7ddd7b6a1f90c from last year which added the
ID_AA64MMFR3_EL1 register.)

thanks
-- PMM

Peter Maydell (2):
  target/arm: Move ID register field defs to cpu-features.h
  target/arm: Implement ID_AA64PFR2_EL1

 linux-user/arm/target_proc.h |   2 +
 target/arm/cpu-features.h    | 414 +++++++++++++++++++++++++++++++++++
 target/arm/cpu.h             | 410 +---------------------------------
 target/arm/helper.c          |   6 +-
 target/arm/hvf/hvf.c         |   2 +
 target/arm/kvm.c             |   2 +
 6 files changed, 425 insertions(+), 411 deletions(-)