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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a5324361ffsm9098991f8f.47.2025.06.09.03.41.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jun 2025 03:41:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/2] target/arm: Implement ID_AA64PFR2_EL1 Date: Mon, 9 Jun 2025 11:41:44 +0100 Message-ID: <20250609104146.1547437-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ID register ID_AA64PFR2_EL1 is in the space previously reserved in the system register ID space, but recent versions of the architecture have started to define fields in it to advertise the presence of new architectural features. We don't implement any of those new features yet, but will need to do so at some point. (Notably, the GICv5 beta spec defines a field in this register to advertise the GICv5 CPU interface.) This patchset gives ID_AA64PFR2_EL1 a backing field in the CPU ID regs struct, defines the field names, and reads it from KVM if it's present there. The only visible behaviour change is the name we present to the user via the gdbstub. Commit 1 is a code movement one to clear some more stuff out of cpu.h that doesn't need to be there; it's mostly because of that that I'm sending this patchset rather than holding on to it until I have some GICv5 patches ready to send. (Compare commit f7ddd7b6a1f90c from last year which added the ID_AA64MMFR3_EL1 register.) thanks -- PMM Peter Maydell (2): target/arm: Move ID register field defs to cpu-features.h target/arm: Implement ID_AA64PFR2_EL1 linux-user/arm/target_proc.h | 2 + target/arm/cpu-features.h | 414 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 410 +--------------------------------- target/arm/helper.c | 6 +- target/arm/hvf/hvf.c | 2 + target/arm/kvm.c | 2 + 6 files changed, 425 insertions(+), 411 deletions(-)