Show patches with: Series = target/arm: Convert a64 advsimd to decodetree (part 1b)       |    State = Action Required       |   10 patches
Patch Series S/W/F Date Submitter Delegate State
[v3,30/33] target/arm: Tidy SQDMULH, SQRDMULH (vector) target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,22/33] target/arm: Convert SHSUB, UHSUB to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,20/33] target/arm: Convert SHADD, UHADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,14/33] target/arm: Convert SQRSHL and UQRSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,12/33] target/arm: Convert SQSHL and UQSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,10/33] target/arm: Convert SRSHL and URSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,06/33] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,05/33] target/arm: Inline scalar SUQADD and USQADD target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,04/33] target/arm: Convert SUQADD and USQADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,01/33] target/arm: Diagnose UNPREDICTABLE operands to PLD, PLDW, PLI target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New