Show patches with: Series = target/arm: Convert a64 advsimd to decodetree (part 1b)       |   33 patches
Patch Series S/W/F Date Submitter Delegate State
[v3,33/33] target/arm: Convert FCSEL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,32/33] target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,31/33] target/arm: Convert SQDMULH, SQRDMULH to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,30/33] target/arm: Tidy SQDMULH, SQRDMULH (vector) target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,29/33] target/arm: Convert MLA, MLS to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,28/33] target/arm: Convert MUL, PMUL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,27/33] target/arm: Convert SABA, SABD, UABA, UABD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,26/33] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,25/33] target/arm: Convert SRHADD, URHADD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,24/33] target/arm: Convert SRHADD, URHADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Accepted
[v3,23/33] target/arm: Convert SHSUB, UHSUB to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,22/33] target/arm: Convert SHSUB, UHSUB to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,21/33] target/arm: Convert SHADD, UHADD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,20/33] target/arm: Convert SHADD, UHADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,19/33] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,18/33] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64} target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,17/33] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,16/33] target/arm: Convert ADD, SUB (vector) to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,15/33] target/arm: Convert SQRSHL, UQRSHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,14/33] target/arm: Convert SQRSHL and UQRSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,13/33] target/arm: Convert SQSHL, UQSHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,12/33] target/arm: Convert SQSHL and UQSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,11/33] target/arm: Convert SRSHL, URSHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,10/33] target/arm: Convert SRSHL and URSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,09/33] target/arm: Convert SSHL, USHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,08/33] target/arm: Convert SUQADD, USQADD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,07/33] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,06/33] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,05/33] target/arm: Inline scalar SUQADD and USQADD target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,04/33] target/arm: Convert SUQADD and USQADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New
[v3,03/33] target/arm: Assert oprsz in range when using vfp.qc target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,02/33] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson Superseded
[v3,01/33] target/arm: Diagnose UNPREDICTABLE operands to PLD, PLDW, PLI target/arm: Convert a64 advsimd to decodetree (part 1b) --- 2024-05-28 Richard Henderson New