Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   26 patches
Patch Series S/W/F Date Submitter Delegate State
[PULL,23/54] hw/riscv/virt: Restrict ACLINT to TCG Untitled series #214799 --- 2023-07-10 Alistair Francis New
[PULL,21/54] target/riscv: Only build KVM guest with same wordsize as host Untitled series #214799 --- 2023-07-10 Alistair Francis New
[PULL,20/54] target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson Untitled series #214799 --- 2023-07-10 Alistair Francis New
[PULL,30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Untitled series #212477 --- 2023-06-14 Alistair Francis New
[PULL,29/60] hw/riscv/opentitan: Explicit machine type definition Untitled series #212477 --- 2023-06-14 Alistair Francis New
[PULL,28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Untitled series #212477 --- 2023-06-14 Alistair Francis New
[PULL,27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Untitled series #212477 --- 2023-06-14 Alistair Francis New
[PULL,26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Untitled series #212477 --- 2023-06-14 Alistair Francis New
[PULL,81/89] target/riscv: Reorg sum check in get_physical_address Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,80/89] target/riscv: Reorg access check in get_physical_address Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,79/89] target/riscv: Merge checks for reserved pte flags Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,78/89] target/riscv: Don't modify SUM with is_debug Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,77/89] target/riscv: Suppress pte update with is_debug Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,76/89] target/riscv: Move leaf pte processing out of level loop Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,75/89] target/riscv: Hoist pbmte and hade out of the level loop Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,74/89] target/riscv: Hoist second stage mode change to callers Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,73/89] target/riscv: Check SUM in the correct register Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,70/89] target/riscv: Introduce mmuidx_2stage Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,69/89] target/riscv: Introduce mmuidx_priv Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,68/89] target/riscv: Introduce mmuidx_sum Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,66/89] target/riscv: Handle HLV, HSV via helpers Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Untitled series #208652 --- 2023-05-05 Alistair Francis New
[PULL,61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Untitled series #208652 --- 2023-05-05 Alistair Francis New