From patchwork Tue Dec 11 16:11:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13480 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6AD3F23FE4 for ; Tue, 11 Dec 2012 16:11:44 +0000 (UTC) Received: from mail-ia0-f178.google.com (mail-ia0-f178.google.com [209.85.210.178]) by fiordland.canonical.com (Postfix) with ESMTP id 1B04CA196B4 for ; Tue, 11 Dec 2012 16:11:44 +0000 (UTC) Received: by mail-ia0-f178.google.com with SMTP id k25so8340058iah.23 for ; Tue, 11 Dec 2012 08:11:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=R4PiB9vdoXg73Rkt7KMPidvdoifnX9URwdukV5LsucI=; b=OTJ3KAllJrZqBjmyyYOtPr/7e1+cXfn6krGh7Jtb6CRe2W+3dBnbRToSHqfw2zk4p6 lC2HZ6MKHFL2dzlyvNZy4v03BYJhtUxOX/9J/QXm5C8wLihfs0yR/IUn8uAuMefYfrk5 jH84QCQHp8PejU9AeibwlNOJ3L3pWcK07wRu/GlnIMJy2mxO9EDf3zpZ+ZjohsunB8Fx fvplwE2qiNhLifOIBp5FUGZzRt49kPKB4cnqk3fBQ8p5je0hJDGElGxKnHAX4jjm+u2R gUtl8L882JgKR+/Ygf/PhvFuUGL/ZJo4gODRwzdohL9m6fEr7A60GX5vqPl9oty9Vgcb iKJA== Received: by 10.50.213.69 with SMTP id nq5mr3076909igc.70.1355242303490; Tue, 11 Dec 2012 08:11:43 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp141881igt; Tue, 11 Dec 2012 08:11:42 -0800 (PST) Received: by 10.180.87.39 with SMTP id u7mr17578089wiz.6.1355242302258; Tue, 11 Dec 2012 08:11:42 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id c59si17055764weq.100.2012.12.11.08.11.41 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 11 Dec 2012 08:11:42 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TiSQl-0007ek-4k; Tue, 11 Dec 2012 16:11:39 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes Date: Tue, 11 Dec 2012 16:11:39 +0000 Message-Id: <1355242299-29407-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQkIcwpbPmX+R4bqIguvItaZqPTcRD2bupL5gKX2hmXXQwBmjGJGd5zonX59OqKe0zTW0Vnm Fix a leak of a TCG temporary in code paths for VFP system register writes for cases which UNDEF or are write-ignored. Signed-off-by: Peter Maydell --- target-arm/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 3cf3604..d6fafa0 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2737,7 +2737,6 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) } } else { /* arm->vfp */ - tmp = load_reg(s, rd); if (insn & (1 << 21)) { rn >>= 1; /* system register */ @@ -2748,6 +2747,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) /* Writes are ignored. */ break; case ARM_VFP_FPSCR: + tmp = load_reg(s, rd); gen_helper_vfp_set_fpscr(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_lookup_tb(s); @@ -2757,18 +2757,21 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) return 1; /* TODO: VFP subarchitecture support. * For now, keep the EN bit only */ + tmp = load_reg(s, rd); tcg_gen_andi_i32(tmp, tmp, 1 << 30); store_cpu_field(tmp, vfp.xregs[rn]); gen_lookup_tb(s); break; case ARM_VFP_FPINST: case ARM_VFP_FPINST2: + tmp = load_reg(s, rd); store_cpu_field(tmp, vfp.xregs[rn]); break; default: return 1; } } else { + tmp = load_reg(s, rd); gen_vfp_msr(tmp); gen_mov_vreg_F0(0, rn); }