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[82.1.113.198]) by mx.google.com with ESMTPSA id jw4sm971156wjc.20.2014.01.14.08.43.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jan 2014 08:43:27 -0800 (PST) From: Will Newton To: qemu-devel@nongnu.org Date: Tue, 14 Jan 2014 16:43:07 +0000 Message-Id: <1389717790-30860-7-git-send-email-will.newton@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1389717790-30860-1-git-send-email-will.newton@linaro.org> References: <1389717790-30860-1-git-send-email-will.newton@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.48 Cc: Peter Maydell Subject: [Qemu-devel] [PATCH 6/9] target-arm: Add support for AArch32 SIMD VRINTX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.newton@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: Will Newton Reviewed-by: Peter Maydell --- target-arm/translate.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 5108f6b..b6d11db 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4709,6 +4709,7 @@ static const uint8_t neon_3r_sizes[] = { #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ #define NEON_2RM_VSHLL 38 +#define NEON_2RM_VRINTX 41 #define NEON_2RM_VCVT_F16_F32 44 #define NEON_2RM_VCVT_F32_F16 46 #define NEON_2RM_VRECPE 56 @@ -4724,7 +4725,7 @@ static int neon_2rm_is_float_op(int op) { /* Return true if this neon 2reg-misc op is float-to-float */ return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || - op >= NEON_2RM_VRECPE_F); + op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F); } /* Each entry in this array has bit n set if the insn allows @@ -4768,6 +4769,7 @@ static const uint8_t neon_2rm_sizes[] = { [NEON_2RM_VMOVN] = 0x7, [NEON_2RM_VQMOVN] = 0x7, [NEON_2RM_VSHLL] = 0x7, + [NEON_2RM_VRINTX] = 0x4, [NEON_2RM_VCVT_F16_F32] = 0x2, [NEON_2RM_VCVT_F32_F16] = 0x2, [NEON_2RM_VRECPE] = 0x4, @@ -6480,6 +6482,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins } neon_store_reg(rm, pass, tmp2); break; + case NEON_2RM_VRINTX: + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus); + tcg_temp_free_ptr(fpstatus); + break; + } case NEON_2RM_VRECPE: gen_helper_recpe_u32(tmp, tmp, cpu_env); break;