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[82.1.113.198]) by mx.google.com with ESMTPSA id a8sm22366424lae.5.2014.01.28.03.22.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jan 2014 03:22:45 -0800 (PST) From: Will Newton To: qemu-devel@nongnu.org Cc: Peter Maydell , patches@linaro.org Subject: [PATCH v2 04/11] target-arm: Add support for AArch32 FP VRINTZ Date: Tue, 28 Jan 2014 11:22:28 +0000 Message-Id: <1390908155-23475-4-git-send-email-will.newton@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1390908155-23475-1-git-send-email-will.newton@linaro.org> References: <1390908155-23475-1-git-send-email-will.newton@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.newton@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for the AArch32 floating-point VRINTZ instruction. Signed-off-by: Will Newton --- target-arm/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) Changes in v2: - Move code outside the arms of the if diff --git a/target-arm/translate.c b/target-arm/translate.c index 2b3157c..9afb19f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3390,6 +3390,22 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_temp_free_ptr(fpst); break; } + case 13: /* vrintz */ + { + TCGv_ptr fpst = get_fpstatus_ptr(0); + TCGv_i32 tcg_rmode; + tcg_rmode = tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + if (dp) { + gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); + } else { + gen_helper_rints(cpu_F0s, cpu_F0s, fpst); + } + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_ptr(fpst); + break; + } case 15: /* single<->double conversion */ if (dp) gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);