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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id fy2si4621466wib.56.2014.04.10.09.15.42 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 10 Apr 2014 09:15:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WYHda-0007sX-CL; Thu, 10 Apr 2014 17:15:38 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Peter Crosthwaite , Greg Bellows Subject: [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc Date: Thu, 10 Apr 2014 17:15:35 +0100 Message-Id: <1397146536-30116-37-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1397146536-30116-1-git-send-email-peter.maydell@linaro.org> References: <1397146536-30116-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The AArch64 implementation of the set_pc method needs to be updated to handle the possibility that the CPU is in AArch32 mode; otherwise there are weird crashes when doing interprocessing in system emulation mode when an interrupt occurs and we fail to resynchronize the 32-bit PC with the TB we need to execute next. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Peter Crosthwaite --- target-arm/cpu64.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 9a0c431..c673ac2 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -172,11 +172,15 @@ static void aarch64_cpu_finalizefn(Object *obj) static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu = ARM_CPU(cs); - /* - * TODO: this will need updating for system emulation, - * when the core may be in AArch32 mode. + /* It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + * (Otherwise we would need to use synchronize_from_tb instead.) */ - cpu->env.pc = value; + if (is_a64(&cpu->env)) { + cpu->env.pc = value; + } else { + cpu->env.regs[15] = value; + } } static void aarch64_cpu_class_init(ObjectClass *oc, void *data)