From patchwork Tue May 27 16:28:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 31006 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f197.google.com (mail-vc0-f197.google.com [209.85.220.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4A71E2066E for ; Tue, 27 May 2014 16:37:55 +0000 (UTC) Received: by mail-vc0-f197.google.com with SMTP id id10sf26717039vcb.8 for ; Tue, 27 May 2014 09:37:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=E4QTvidmT+vS4i3BAVWsiAqtyklKpw/XD7RWmbXGwkQ=; b=WTv+L6Xyt41qJrZ4MslGnqN3tIn7rYZr7UVr6xap7wMlW/X7AzeckRVLgEA5o9QD3h AQkrCpkuF5Aq2LWivqbuurGtVCRPcTRbFHsjgXz10bBsbZwqVST2XS0Y16gBfWsMGKz8 OlKyzxFCkGEh0izF6Bz4govHPqMqhbcD6Bc/Lw3YlhnUrGZDx4mVAsODbkMtA+BWsSnT iE0If9n4YeVlWoopUnZaiT/g8JYiIq8GzpC6lwS2FEZ3Pdq+I8YdJ1xzHLA6anzf/JJt tfBhsaaVHZ+XyFxgkG1Dri0yH0BjAeoSkWYq6hf+9f0yoDc+7J7ZQCLULKukd7KKDPYR OL8A== X-Gm-Message-State: ALoCoQneFJcvdoLmPazTHNDVTBiltCcfS6t4JmW0fYZgurwGPvwUq4layiRg41l339/wbIXviuax X-Received: by 10.236.136.66 with SMTP id v42mr11955115yhi.24.1401208675086; Tue, 27 May 2014 09:37:55 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.34.46 with SMTP id k43ls3219241qgk.58.gmail; Tue, 27 May 2014 09:37:55 -0700 (PDT) X-Received: by 10.52.107.33 with SMTP id gz1mr1781417vdb.72.1401208675021; Tue, 27 May 2014 09:37:55 -0700 (PDT) Received: from mail-ve0-f179.google.com (mail-ve0-f179.google.com [209.85.128.179]) by mx.google.com with ESMTPS id xe6si8499752vcb.28.2014.05.27.09.37.54 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 27 May 2014 09:37:54 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.179 as permitted sender) client-ip=209.85.128.179; Received: by mail-ve0-f179.google.com with SMTP id oy12so10991188veb.38 for ; Tue, 27 May 2014 09:37:54 -0700 (PDT) X-Received: by 10.220.44.141 with SMTP id a13mr1937461vcf.71.1401208674928; Tue, 27 May 2014 09:37:54 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp133399vcb; Tue, 27 May 2014 09:37:54 -0700 (PDT) X-Received: by 10.224.54.68 with SMTP id p4mr43001657qag.47.1401208674431; Tue, 27 May 2014 09:37:54 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 18si17721096qgs.8.2014.05.27.09.37.54 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 27 May 2014 09:37:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:36581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpKNt-00009I-EQ for patch@linaro.org; Tue, 27 May 2014 12:37:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpKF9-0003H2-9L for qemu-devel@nongnu.org; Tue, 27 May 2014 12:28:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WpKF8-0002t9-8W for qemu-devel@nongnu.org; Tue, 27 May 2014 12:28:51 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48252) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WpKF8-0002lf-0V for qemu-devel@nongnu.org; Tue, 27 May 2014 12:28:50 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WpKEs-0005q8-H2; Tue, 27 May 2014 17:28:34 +0100 From: Peter Maydell To: Anthony Liguori Date: Tue, 27 May 2014 17:28:13 +0100 Message-Id: <1401208114-22404-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1401208114-22404-1-git-send-email-peter.maydell@linaro.org> References: <1401208114-22404-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Clean up the mmu index handling for ldrt/strt insns: instead of a flag 'user' indicating whether to treat the store as user mode or not, use 'memidx' to indicate the correct memory index to use. Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell Message-id: 1400980132-25949-3-git-send-email-edgar.iglesias@gmail.com --- target-arm/translate.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index a4d920b..e708f4a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8568,7 +8568,12 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; tmp2 = load_reg(s, rn); - i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000); + if ((insn & 0x01200000) == 0x00200000) { + /* ldrt/strt */ + i = MMU_USER_IDX; + } else { + i = get_mem_index(s); + } if (insn & (1 << 24)) gen_add_data_offset(s, insn, tmp2); if (insn & (1 << 20)) { @@ -9841,7 +9846,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw { int postinc = 0; int writeback = 0; - int user; + int memidx; if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(env, s, insn)) goto illegal_op; @@ -9885,7 +9890,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw return 1; } } - user = IS_USER(s); + memidx = get_mem_index(s); if (rn == 15) { addr = tcg_temp_new_i32(); /* PC relative. */ @@ -9922,7 +9927,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw break; case 0xe: /* User privilege. */ tcg_gen_addi_i32(addr, addr, imm); - user = 1; + memidx = MMU_USER_IDX; break; case 0x9: /* Post-decrement. */ imm = -imm; @@ -9949,19 +9954,19 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = tcg_temp_new_i32(); switch (op) { case 0: - gen_aa32_ld8u(tmp, addr, user); + gen_aa32_ld8u(tmp, addr, memidx); break; case 4: - gen_aa32_ld8s(tmp, addr, user); + gen_aa32_ld8s(tmp, addr, memidx); break; case 1: - gen_aa32_ld16u(tmp, addr, user); + gen_aa32_ld16u(tmp, addr, memidx); break; case 5: - gen_aa32_ld16s(tmp, addr, user); + gen_aa32_ld16s(tmp, addr, memidx); break; case 2: - gen_aa32_ld32u(tmp, addr, user); + gen_aa32_ld32u(tmp, addr, memidx); break; default: tcg_temp_free_i32(tmp); @@ -9978,13 +9983,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp = load_reg(s, rs); switch (op) { case 0: - gen_aa32_st8(tmp, addr, user); + gen_aa32_st8(tmp, addr, memidx); break; case 1: - gen_aa32_st16(tmp, addr, user); + gen_aa32_st16(tmp, addr, memidx); break; case 2: - gen_aa32_st32(tmp, addr, user); + gen_aa32_st32(tmp, addr, memidx); break; default: tcg_temp_free_i32(tmp);