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X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The ARM ARM requires that the FPINST and FPINST2 VFP control registers are not accessible to code at EL0. We were already correctly implementing this for reads of these registers; add the missing check for the write code path. Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 1412967447-20931-1-git-send-email-peter.maydell@linaro.org --- target-arm/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 4e764d3..656b09e 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3232,6 +3232,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) break; case ARM_VFP_FPINST: case ARM_VFP_FPINST2: + if (IS_USER(s)) { + return 1; + } tmp = load_reg(s, rd); store_cpu_field(tmp, vfp.xregs[rn]); break;