From patchwork Wed Nov 5 23:23:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40229 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f71.google.com (mail-wg0-f71.google.com [74.125.82.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6A8F9240A6 for ; Wed, 5 Nov 2014 23:27:22 +0000 (UTC) Received: by mail-wg0-f71.google.com with SMTP id b13sf1081410wgh.10 for ; Wed, 05 Nov 2014 15:27:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=991xRYmR8a7RTpKsBrNtJUyC7l9s7J9c/frBt8/eu7E=; b=Yl32vra3VcExUvJY23h+fbgMF6oOmiqdEHBac7HQIfF09RBqJ7YfopFzIwaPXNppjK 4tcrqYx/tnqm/5YQtSnAudfyLSILwlTMTATnMDXLNYOm7Av7rO4p7rfwEKzBNcuyjC4b yjT+BiTDOftJntiWdydhVtcpEhORsIhzKGLnc9cJvxiiAlaOotHkjuoeIM+ojnTVnsaE 1whOu7mSb0x4so5wqVBH6LuLy9HAgcZHNAOQc0WGxRQ1UC1oUZ/DEoSQ8OoEKAzS7lBh sAfZoAu/X53ubdt8lQRqNG8e6+ail2UyZGFMJ974LyfNoygU/Crro+tDDaVGhDBBB79F UqvQ== X-Gm-Message-State: ALoCoQmGPlhcwOnk1DKmnk4OJ9J40Pn3EU3Z/9oppeMIu8XV83wG3vfrVf7FdaGKXe0cZo8Sa8AS X-Received: by 10.180.81.5 with SMTP id v5mr3667788wix.0.1415230041656; Wed, 05 Nov 2014 15:27:21 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.153.4.33 with SMTP id cb1ls8630lad.89.gmail; Wed, 05 Nov 2014 15:27:21 -0800 (PST) X-Received: by 10.152.115.131 with SMTP id jo3mr672955lab.20.1415230041485; Wed, 05 Nov 2014 15:27:21 -0800 (PST) Received: from mail-la0-f50.google.com (mail-la0-f50.google.com. [209.85.215.50]) by mx.google.com with ESMTPS id o7si8783833lao.40.2014.11.05.15.27.21 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:27:21 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) client-ip=209.85.215.50; Received: by mail-la0-f50.google.com with SMTP id hz20so1630141lab.37 for ; Wed, 05 Nov 2014 15:27:21 -0800 (PST) X-Received: by 10.112.202.104 with SMTP id kh8mr657613lbc.46.1415230041339; Wed, 05 Nov 2014 15:27:21 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp371580lbc; Wed, 5 Nov 2014 15:27:20 -0800 (PST) X-Received: by 10.224.122.80 with SMTP id k16mr1032501qar.40.1415230039742; Wed, 05 Nov 2014 15:27:19 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m2si8603845qab.62.2014.11.05.15.27.19 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:27:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:48971 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9yw-00019P-TN for patch@linaro.org; Wed, 05 Nov 2014 18:27:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56567) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vm-0004nl-5B for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:24:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vg-0004jv-SY for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:24:02 -0500 Received: from mail-pa0-f43.google.com ([209.85.220.43]:37405) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vg-0004jn-KF for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:56 -0500 Received: by mail-pa0-f43.google.com with SMTP id eu11so1752444pac.30 for ; Wed, 05 Nov 2014 15:23:56 -0800 (PST) X-Received: by 10.68.68.144 with SMTP id w16mr436957pbt.162.1415229836054; Wed, 05 Nov 2014 15:23:56 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:55 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:23:09 -0600 Message-Id: <1415229793-3278-23-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.43 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 22/26] target-arm: make PAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Cleaned-up ats_write() to only call A32_BANKED_CURRENT_REG_SET() once at the endof the function. - Revert unnecessary CPreg definition changes v5 -> v6 - Changed _el field variants to be array based v3 -> v4 - Fix par union/structure definition --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 23 +++++++++++++---------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index bdd3366..a991f85 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -279,7 +279,15 @@ typedef struct CPUARMState { }; uint64_t far_el[4]; }; - uint64_t par_el1; /* Translation result. */ + union { /* Translation result. */ + struct { + uint64_t _unused_par_0; + uint64_t par_ns; + uint64_t _unused_par_1; + uint64_t par_s; + }; + uint64_t par_el[4]; + }; uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 7f36d55..fa4ad05 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1404,6 +1404,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) int prot; int ret, is_user = ri->opc2 & 2; int access_type = ri->opc2 & 1; + uint64_t par64; ret = get_phys_addr(env, value, access_type, is_user, &phys_addr, &prot, &page_size); @@ -1412,7 +1413,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) * translation table format, but with WnR always clear. * Convert it to a 64-bit PAR. */ - uint64_t par64 = (1 << 11); /* LPAE bit always set */ + par64 = (1 << 11); /* LPAE bit always set */ if (ret == 0) { par64 |= phys_addr & ~0xfffULL; /* We don't set the ATTR or SH fields in the PAR. */ @@ -1424,7 +1425,6 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) * fault. */ } - env->cp15.par_el1 = par64; } else { /* ret is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). @@ -1434,23 +1434,25 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* We do not set any attribute bits in the PAR */ if (page_size == (1 << 24) && arm_feature(env, ARM_FEATURE_V7)) { - env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1; + par64 = (phys_addr & 0xff000000) | (1 << 1); } else { - env->cp15.par_el1 = phys_addr & 0xfffff000; + par64 = phys_addr & 0xfffff000; } } else { - env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) | - ((ret & (1 << 12)) >> 6) | - ((ret & 0xf) << 1) | 1; + par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) | + ((ret & 0xf) << 1) | 1; } } + + A32_BANKED_CURRENT_REG_SET(env, par, par64); } #endif static const ARMCPRegInfo vapa_cp_reginfo[] = { { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .resetvalue = 0, - .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), + offsetoflow32(CPUARMState, cp15.par_ns) }, .writefn = par_write }, #ifndef CONFIG_USER_ONLY { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, @@ -1903,8 +1905,9 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, - .access = PL1_RW, .type = ARM_CP_64BIT, - .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, + .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), + offsetof(CPUARMState, cp15.par_ns)} }, { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),