From patchwork Wed Nov 5 23:22:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40226 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f69.google.com (mail-wg0-f69.google.com [74.125.82.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DF6FB240A6 for ; Wed, 5 Nov 2014 23:26:55 +0000 (UTC) Received: by mail-wg0-f69.google.com with SMTP id l18sf1085421wgh.4 for ; Wed, 05 Nov 2014 15:26:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=EsC1ahmK4cXZWDL4AJNBJdoJiewvKC16KbirXZaxP3Q=; b=SJYpfKOdwK0+u53uwh5kSQhbftl9SCGABkwIPbJAhNdWq2gjNS43+XxeYfcY18ygWZ t3mNCAJJLRPcMXT8aSuM3A30Vub3Ac6AggmwK1mtS6Wkjkvuu1PuuT8kt4bbBdyaJjh6 Ev06qa2KSHZuu/iO4A4EyAtsFdIORNqXsZ9YdYQgwG1UkTDF1dyBtJG0bgJvwWegIL+Y tgkkep0y7xpj1L++m8Xs8ya1eyABtMUxaaxdF/hjcaJF6r1hsZtxRb0bNBs3fXm2TtJN Ca+coBNEKrqDjXownRdLozFypk9AhHK7Z03CqWGEmB0/eYILvp7FHMYM+gWtdV17LVwx xmow== X-Gm-Message-State: ALoCoQml2TbAVHTjSiKOmO10McRJ+4gcJ/M3JjIU6TxnM3nZAAK2emioD3cIVui8AQCU3f8IwmSQ X-Received: by 10.112.163.229 with SMTP id yl5mr12102lbb.23.1415230015001; Wed, 05 Nov 2014 15:26:55 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.205.108 with SMTP id lf12ls9318lac.48.gmail; Wed, 05 Nov 2014 15:26:54 -0800 (PST) X-Received: by 10.112.159.129 with SMTP id xc1mr687276lbb.24.1415230014447; Wed, 05 Nov 2014 15:26:54 -0800 (PST) Received: from mail-la0-f47.google.com (mail-la0-f47.google.com. [209.85.215.47]) by mx.google.com with ESMTPS id i3si8735302lae.59.2014.11.05.15.26.54 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:26:54 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) client-ip=209.85.215.47; Received: by mail-la0-f47.google.com with SMTP id gd6so1627275lab.6 for ; Wed, 05 Nov 2014 15:26:54 -0800 (PST) X-Received: by 10.112.189.10 with SMTP id ge10mr539572lbc.23.1415230014204; Wed, 05 Nov 2014 15:26:54 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp371537lbc; Wed, 5 Nov 2014 15:26:53 -0800 (PST) X-Received: by 10.224.4.197 with SMTP id 5mr985070qas.74.1415230012726; Wed, 05 Nov 2014 15:26:52 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 101si9030631qgx.57.2014.11.05.15.26.52 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:26:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:48968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9yV-0000JD-RP for patch@linaro.org; Wed, 05 Nov 2014 18:26:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vM-00042w-Uk for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vH-0004bq-1F for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:36 -0500 Received: from mail-pd0-f172.google.com ([209.85.192.172]:42726) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vG-0004bj-Op for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:30 -0500 Received: by mail-pd0-f172.google.com with SMTP id r10so1707486pdi.3 for ; Wed, 05 Nov 2014 15:23:30 -0800 (PST) X-Received: by 10.66.191.135 with SMTP id gy7mr360812pac.95.1415229810048; Wed, 05 Nov 2014 15:23:30 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.28 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:29 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:22:53 -0600 Message-Id: <1415229793-3278-7-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.172 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 06/26] target-arm: add secure state bit to CPREG hash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Added additional NS-bit to CPREG hash encoding. Updated hash lookup locations to specify hash bit currently set to non-secure. Signed-off-by: Greg Bellows --- v8 -> v9 - Fixed CP_REG_NS_MASK - Changed ENCODE_CP_REG argument order so ns follows is64 - Replaced use of CP_REG_NS_MASK with CP_REG_NS_SHIFT - Changed add_cpreg_to_hashtable argument order so ns follows is64 - Replaced use of SCR_NS with ARM_CP_SECSTATE_NS on registration - Undid global replace of Aarch# with AArch# in translate.c v5 -> v6 - Globally replace Aarch# with AArch# --- target-arm/cpu.h | 25 ++++++++++++++++++++----- target-arm/helper.c | 7 ++++--- target-arm/translate.c | 14 +++++++++----- 3 files changed, 33 insertions(+), 13 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a9cbfc7..3031911 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -879,6 +879,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq); * Crn, Crm, opc1, opc2 fields * 32 or 64 bit register (ie is it accessed via MRC/MCR * or via MRRC/MCRR?) + * non-secure/secure bank (AArch32 only) * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. * (In this case crn and opc2 should be zero.) * For AArch64, there is no 32/64 bit size distinction; @@ -896,9 +897,16 @@ void armv7m_nvic_complete_irq(void *opaque, int irq); #define CP_REG_AA64_SHIFT 28 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) -#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ - (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ - ((crm) << 7) | ((opc1) << 3) | (opc2)) +/* To enable banking of coprocessor registers depending on ns-bit we + * add a bit to distinguish between secure and non-secure cpregs in the + * hashtable. + */ +#define CP_REG_NS_SHIFT 29 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) + +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ (CP_REG_AA64_MASK | \ @@ -917,8 +925,15 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) uint32_t cpregid = kvmid; if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { cpregid |= CP_REG_AA64_MASK; - } else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { - cpregid |= (1 << 15); + } else { + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { + cpregid |= (1 << 15); + } + + /* KVM is always non-secure so add the NS flag on AArch32 register + * entries. + */ + cpregid |= 1 << CP_REG_NS_SHIFT; } return cpregid; } diff --git a/target-arm/helper.c b/target-arm/helper.c index a48ebae..1aadb79 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3287,7 +3287,7 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) } static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, + void *opaque, int state, int secstate, int crm, int opc1, int opc2) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): @@ -3296,6 +3296,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, uint32_t *key = g_new(uint32_t, 1); ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; + int ns = (r->secure & ARM_CP_SECSTATE_NS) ? 1 : 0; if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { /* The AArch32 view of a shared register sees the lower 32 bits * of a 64 bit backing field. It is not migratable as the AArch64 @@ -3327,7 +3328,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, r2->opc0, opc1, opc2); } else { - *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); + *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); } if (opaque) { r2->opaque = opaque; @@ -3477,7 +3478,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, continue; } add_cpreg_to_hashtable(cpu, r, opaque, state, - crm, opc1, opc2); + ARM_CP_SECSTATE_NS, crm, opc1, opc2); } } } diff --git a/target-arm/translate.c b/target-arm/translate.c index 32eb7bb..0f63aa5 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7074,7 +7074,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) rt = (insn >> 12) & 0xf; ri = get_arm_cp_reginfo(s->cp_regs, - ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2)); + ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { @@ -7264,12 +7264,16 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) */ if (is64) { qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 " - "64 bit system register cp:%d opc1: %d crm:%d\n", - isread ? "read" : "write", cpnum, opc1, crm); + "64 bit system register cp:%d opc1: %d crm:%d " + "(%s)\n", + isread ? "read" : "write", cpnum, opc1, crm, + s->ns ? "non-secure" : "secure"); } else { qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 " - "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n", - isread ? "read" : "write", cpnum, opc1, crn, crm, opc2); + "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d " + "(%s)\n", + isread ? "read" : "write", cpnum, opc1, crn, crm, opc2, + s->ns ? "non-secure" : "secure"); } return 1;