From patchwork Thu Nov 6 15:50:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40340 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 438F420C4E for ; Thu, 6 Nov 2014 15:59:42 +0000 (UTC) Received: by mail-wi0-f200.google.com with SMTP id h11sf858211wiw.7 for ; Thu, 06 Nov 2014 07:59:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=0hFXK8BUJ/0nIaZ/HNKeTqTV9DzNbQK3dzypnBYCWcM=; b=fomuhO7RdiWCAJBLRWImnR7kK6dbR5w4jQ/UQ+bRjvOFKhmxCUSSaVjywBwX9DzAzM wmU0XvIs9Wr41kamnquR5gnKTkRF7cx0LsGqYlgLyQGSHQTtOw1gdQ+XEN2iuUzEjt1h h9Z5IvkQ03oAfydmsCwvCAWHWL5ibgfyFwXoiwivfRDQ/SPpmfamAxiNGYjyYcNu6tzk Xo6pswGFhPCffRMBXPb6adB79Gx5ZdjdDYcQJJirxqzYBvPw4qB6tQBg3ApHxI7AmHUI GVHjowudcl8qqTRJnnKuDE1v6V2HC/H+wgnb3ys6C92BQCGZfkUGUR7DEsmzA7MMUjRQ dCBQ== X-Gm-Message-State: ALoCoQl5M0JwRaBEjf72RRvonIh5sJRQH244vQmlSfDT02G5wrNz3bDoeGxRAgWRgeNlahXFKxpG X-Received: by 10.180.104.233 with SMTP id gh9mr705783wib.4.1415289581435; Thu, 06 Nov 2014 07:59:41 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.38 with SMTP id p6ls102978lap.64.gmail; Thu, 06 Nov 2014 07:59:41 -0800 (PST) X-Received: by 10.152.43.97 with SMTP id v1mr5805374lal.3.1415289581208; Thu, 06 Nov 2014 07:59:41 -0800 (PST) Received: from mail-lb0-f171.google.com (mail-lb0-f171.google.com. [209.85.217.171]) by mx.google.com with ESMTPS id j9si12017271lab.13.2014.11.06.07.59.41 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:59:41 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) client-ip=209.85.217.171; Received: by mail-lb0-f171.google.com with SMTP id b6so1148850lbj.30 for ; Thu, 06 Nov 2014 07:59:41 -0800 (PST) X-Received: by 10.152.5.38 with SMTP id p6mr5817619lap.44.1415289581120; Thu, 06 Nov 2014 07:59:41 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp66304lbc; Thu, 6 Nov 2014 07:59:40 -0800 (PST) X-Received: by 10.224.123.132 with SMTP id p4mr8000511qar.3.1415289579647; Thu, 06 Nov 2014 07:59:39 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y20si12340356qay.99.2014.11.06.07.59.39 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:59:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:54622 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPTG-0005vi-Qj for patch@linaro.org; Thu, 06 Nov 2014 10:59:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLl-0001sp-Ii for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLf-0004Ia-IC for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:53 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:48398) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLf-0004IU-Db for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:47 -0500 Received: by mail-pa0-f49.google.com with SMTP id lj1so1477975pab.22 for ; Thu, 06 Nov 2014 07:51:47 -0800 (PST) X-Received: by 10.70.130.47 with SMTP id ob15mr5309171pdb.112.1415289106935; Thu, 06 Nov 2014 07:51:46 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.51.44 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:51:45 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:50:58 -0600 Message-Id: <1415289073-14681-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.49 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 11/26] target-arm: add SDER definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Fixed declaration order of the SDER register components v7 -> v8 - Added SDER32_EL3 register definition - Changed sder name from c1_sder to sder - Changed sder from uint32_t to uint64_t. --- target-arm/cpu.h | 1 + target-arm/helper.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 97f952c..7a860e6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 016cf39..cb15ad4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.sder) }, + { .name = "SDER", + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, .access = PL3_W | PL1_R, .resetvalue = 0,