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[209.85.212.170]) by mx.google.com with ESMTPS id pi1si1634492wjb.94.2015.02.12.19.47.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Feb 2015 19:47:23 -0800 (PST) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 209.85.212.170 as permitted sender) client-ip=209.85.212.170; Received: by mail-wi0-f170.google.com with SMTP id hi2so9384901wib.1 for ; Thu, 12 Feb 2015 19:47:23 -0800 (PST) X-Received: by 10.180.76.4 with SMTP id g4mr12108630wiw.43.1423799243381; Thu, 12 Feb 2015 19:47:23 -0800 (PST) Received: from midway01-04-00.lavalab ([81.128.185.50]) by mx.google.com with ESMTPSA id fw5sm8222550wjb.14.2015.02.12.19.47.22 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 12 Feb 2015 19:47:22 -0800 (PST) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, christoffer.dall@linaro.org, qemu-devel@nongnu.org, alex.williamson@redhat.com, peter.maydell@linaro.org, agraf@suse.de, b.reynal@virtualopensystems.com, feng.wu@intel.com Cc: kvmarm@lists.cs.columbia.edu, patches@linaro.org, pbonzini@redhat.com, afaerber@suse.de, kim.phillips@freescale.com, Bharat.Bhushan@freescale.com, a.rigo@virtualopensystems.com, a.motakis@virtualopensystems.com Subject: [PATCH v10 1/7] linux-headers: update VFIO header for VFIO platform drivers Date: Fri, 13 Feb 2015 03:47:06 +0000 Message-Id: <1423799232-10816-2-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1423799232-10816-1-git-send-email-eric.auger@linaro.org> References: <1423799232-10816-1-git-send-email-eric.auger@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: eric.auger@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Update according to vfio.h header found in http://git.linaro.org/people/eric.auger/linux.git branch irqfd_integ_v9 Signed-off-by: Eric Auger --- v9 -> v10: - AMBA removed v8 -> v9: - rewording of the commit message --- linux-headers/linux/vfio.h | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h index 0f21aa6..2ef4485 100644 --- a/linux-headers/linux/vfio.h +++ b/linux-headers/linux/vfio.h @@ -19,22 +19,21 @@ /* Kernel & User level defines for VFIO IOCTLs. */ -/* Extensions */ - -#define VFIO_TYPE1_IOMMU 1 -#define VFIO_SPAPR_TCE_IOMMU 2 -#define VFIO_TYPE1v2_IOMMU 3 /* - * IOMMU enforces DMA cache coherence (ex. PCIe NoSnoop stripping). This - * capability is subject to change as groups are added or removed. + * Capabilities exposed by the VFIO IOMMU driver. Some capabilities are subject + * to change as groups are added or removed. */ -#define VFIO_DMA_CC_IOMMU 4 - -/* Check if EEH is supported */ -#define VFIO_EEH 5 +enum vfio_iommu_cap { + VFIO_TYPE1_IOMMU = 1, + VFIO_SPAPR_TCE_IOMMU = 2, + VFIO_TYPE1v2_IOMMU = 3, + VFIO_DMA_CC_IOMMU = 4, /* IOMMU enforces DMA cache coherence + (ex. PCIe NoSnoop stripping) */ + VFIO_EEH = 5, /* Check if EEH is supported */ + VFIO_TYPE1_NESTING_IOMMU = 6, /* Two-stage IOMMU, implies v2 */ + VFIO_DMA_NOEXEC_IOMMU = 7, +}; -/* Two-stage IOMMU */ -#define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */ /* * The IOCTL interface is designed for extensibility by embedding the @@ -160,6 +159,7 @@ struct vfio_device_info { __u32 flags; #define VFIO_DEVICE_FLAGS_RESET (1 << 0) /* Device supports reset */ #define VFIO_DEVICE_FLAGS_PCI (1 << 1) /* vfio-pci device */ +#define VFIO_DEVICE_FLAGS_PLATFORM (1 << 2) /* vfio-platform device */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ }; @@ -398,12 +398,17 @@ struct vfio_iommu_type1_info { * * Map process virtual addresses to IO virtual addresses using the * provided struct vfio_dma_map. Caller sets argsz. READ &/ WRITE required. + * + * To use the VFIO_DMA_MAP_FLAG_NOEXEC flag, the container must support the + * VFIO_DMA_NOEXEC_IOMMU capability. If mappings are created using this flag, + * any groups subsequently added to the container must support this capability. */ struct vfio_iommu_type1_dma_map { __u32 argsz; __u32 flags; #define VFIO_DMA_MAP_FLAG_READ (1 << 0) /* readable from device */ #define VFIO_DMA_MAP_FLAG_WRITE (1 << 1) /* writable from device */ +#define VFIO_DMA_MAP_FLAG_NOEXEC (1 << 2) /* not executable from device */ __u64 vaddr; /* Process virtual address */ __u64 iova; /* IO virtual address */ __u64 size; /* Size of mapping (bytes) */