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[99.179.1.214]) by mx.google.com with ESMTPSA id x142sm2567707oie.19.2015.04.15.09.02.46 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 15 Apr 2015 09:02:47 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 15 Apr 2015 11:02:16 -0500 Message-Id: <1429113742-8371-11-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.46 Cc: Fabian Aggeler , Greg Bellows Subject: [Qemu-devel] [PATCH v3 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler For GICs with Security Extensions Non-secure reads have a restricted view on the current running priority. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- hw/intc/arm_gic.c | 17 ++++++++++++++++- hw/intc/gic_internal.h | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b62cde2..e65a271 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -314,6 +314,21 @@ void gic_set_cpu_control(GICState *s, int cpu, uint32_t value) } } +uint8_t gic_get_running_priority(GICState *s, int cpu) +{ + if (s->security_extn && ns_access()) { + if (s->running_priority[cpu] & 0x80) { + /* Running priority in upper half, return Non-secure view */ + return s->running_priority[cpu] << 1; + } else { + /* Running priority in lower half, RAZ */ + return 0; + } + } else { + return s->running_priority[cpu]; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -850,7 +865,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x0c: /* Acknowledge */ return gic_acknowledge_irq(s, cpu); case 0x14: /* Running Priority */ - return s->running_priority[cpu]; + return gic_get_running_priority(s, cpu); case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index e360de6..821ce16 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -78,6 +78,7 @@ void gic_init_irqs_and_distributor(GICState *s); void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); uint32_t gic_get_cpu_control(GICState *s, int cpu); void gic_set_cpu_control(GICState *s, int cpu, uint32_t value); +uint8_t gic_get_running_priority(GICState *s, int cpu); static inline bool gic_test_pending(GICState *s, int irq, int cm)