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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id c2si44484664qge.105.2015.11.30.00.46.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 30 Nov 2015 00:46:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:39565 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3K6X-0004Xn-SG for patch@linaro.org; Mon, 30 Nov 2015 03:46:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3K4A-0008Si-Gq for qemu-devel@nongnu.org; Mon, 30 Nov 2015 03:44:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a3K49-0002YU-7p for qemu-devel@nongnu.org; Mon, 30 Nov 2015 03:44:10 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:48392) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3K48-0002Xk-SG; Mon, 30 Nov 2015 03:44:09 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 32DCB140297; Mon, 30 Nov 2015 19:44:07 +1100 (AEDT) From: David Gibson To: peter.maydell@linaro.org Date: Mon, 30 Nov 2015 19:44:43 +1100 Message-Id: <1448873085-9277-4-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1448873085-9277-1-git-send-email-david@gibson.dropbear.id.au> References: <1448873085-9277-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2401:3900:2:1::2 Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, aik@ozlabs.ru, qemu-stable@nongnu.org, agraf@suse.de, mdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org, David Gibson Subject: [Qemu-devel] [PULL 3/5] hw/ppc/ppc405_boards: Fix infinite recursion by converting taihu_cpld from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The taihu_cpld_writel() function had an obvious typo that meant that if it was ever called it would go into an infinite recursion. Newer versions of clang will detect and warn about this: hw/ppc/ppc405_boards.c:481:1: warning: all paths through this function will call itself [-Winfinite-recursion] Fix this by converting taihu_cpld from the legacy old_mmio accessors to new-style ones, with an impl {} declaration to cause the core memory code to do the splitting of 16 bit and 32 bit accesses into multiple 8-bit accesses. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Signed-off-by: David Gibson --- hw/ppc/ppc405_boards.c | 52 ++++++++------------------------------------------ 1 file changed, 8 insertions(+), 44 deletions(-) -- 2.5.0 diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index ec87587..31bc186 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -408,7 +408,7 @@ struct taihu_cpld_t { uint8_t reg1; }; -static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr) +static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) { taihu_cpld_t *cpld; uint32_t ret; @@ -429,8 +429,8 @@ static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr) return ret; } -static void taihu_cpld_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void taihu_cpld_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) { taihu_cpld_t *cpld; @@ -447,48 +447,12 @@ static void taihu_cpld_writeb (void *opaque, } } -static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret = taihu_cpld_readb(opaque, addr) << 8; - ret |= taihu_cpld_readb(opaque, addr + 1); - - return ret; -} - -static void taihu_cpld_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); - taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); -} - -static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret = taihu_cpld_readb(opaque, addr) << 24; - ret |= taihu_cpld_readb(opaque, addr + 1) << 16; - ret |= taihu_cpld_readb(opaque, addr + 2) << 8; - ret |= taihu_cpld_readb(opaque, addr + 3); - - return ret; -} - -static void taihu_cpld_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); - taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); - taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); - taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); -} - static const MemoryRegionOps taihu_cpld_ops = { - .old_mmio = { - .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, - .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, + .read = taihu_cpld_read, + .write = taihu_cpld_write, + .impl = { + .min_access_size = 1, + .max_access_size = 1, }, .endianness = DEVICE_NATIVE_ENDIAN, };