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[34.92.144.28]) by smtp.gmail.com with ESMTPSA id a15sm1397872pju.3.2020.04.30.03.24.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Apr 2020 03:24:54 -0700 (PDT) From: Huacai Chen X-Google-Original-From: Huacai Chen To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic Subject: [PATCH for-5.1 V2 3/7] hw/mips: Add CPU IRQ3 delivery for KVM Date: Thu, 30 Apr 2020 18:22:31 +0800 Message-Id: <1588242155-23924-4-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1588242155-23924-1-git-send-email-chenhc@lemote.com> References: <1588242155-23924-1-git-send-email-chenhc@lemote.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=zltjiangshi@gmail.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Huacai Chen , Aleksandar Rikalo , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP3 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang --- hw/mips/mips_int.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 796730b..5526219 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -48,16 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) kvm_mips_set_interrupt(cpu, irq, level); - } } else { env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) kvm_mips_set_interrupt(cpu, irq, level); - } } if (env->CP0_Cause & CP0Ca_IP_mask) {