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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h8si9972388qkh.112.2016.10.14.08.15.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 14 Oct 2016 08:15:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47860 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bv4Cm-0002BC-No for patch@linaro.org; Fri, 14 Oct 2016 11:15:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bv4BC-0001TD-Tr for qemu-devel@nongnu.org; Fri, 14 Oct 2016 11:13:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bv4B8-0001IN-GO for qemu-devel@nongnu.org; Fri, 14 Oct 2016 11:13:50 -0400 Received: from mail-wm0-x231.google.com ([2a00:1450:400c:c09::231]:37744) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bv4B8-0001I4-2A for qemu-devel@nongnu.org; Fri, 14 Oct 2016 11:13:46 -0400 Received: by mail-wm0-x231.google.com with SMTP id c78so3208906wme.0 for ; Fri, 14 Oct 2016 08:13:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=KkhL1g64376v7t0G0we6IdtX9Wsuo2csNzYAemXQnUU=; b=IVpo6MHWz/V8phTa/Eeu3MyQ0dK1qV42ArkKC9h45qPdzoM3renCzE7VBpSxa4JX4j Au/MoflMCEhEtenSCj5Z+W1z6B8Cjqo1OO+/fSWiFY9OxZ3I1gXd66t/0PxOYsP5veWI lTvSy60/nKRI0+WaLxbXIN9fteNcc/0s3XK7A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=KkhL1g64376v7t0G0we6IdtX9Wsuo2csNzYAemXQnUU=; b=GH12ybC+8KQKKwkCe+D6A2MayIpKJlH+kMRM717PbdZFhjqvRUFpz+YtrN9jr6js+e dQHqFhWcuXk0/RYTUg63SOFjjS7m+6FwFQbyojpYDzZduMlCwCA1YQp8nRdHCnhNQP+7 orxVJ+Zmx3iU5w4Ts+BYO7zHJDjCcbmdgFscGxEpTNr48CYMGaMD4WkWuWxvyWbOpiXM YDERvIWAyjW0thFVu56Q75rXdgxJCa7EgMPMuAwPRwdKnVkEgdwLt8JI5m3UMgE2d5mE lqeygOtHvTCg16vSKcdjGowUsBsQQNLTeGJhyD9yxGpqUjZ6ETkhRJllfiuRy+TlTIPg uziw== X-Gm-Message-State: AA6/9RkzuYxBlscs/uKl/seayNCgd8lBuZuKRFR6VopaQ1B/kvenkmUZUGfTCYc7agXkcYmM X-Received: by 10.194.28.166 with SMTP id c6mr2407633wjh.40.1476458025303; Fri, 14 Oct 2016 08:13:45 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b77sm299733wmb.0.2016.10.14.08.13.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Oct 2016 08:13:44 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 211AC3E00B3; Fri, 14 Oct 2016 16:13:44 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 14 Oct 2016 16:13:36 +0100 Message-Id: <20161014151336.31418-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.9.3 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::231 Subject: [Qemu-devel] [PATCH] target-arm/translate.c: fix movs pc, lr exception return on ARMv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This was broken by the fix for 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0. Specifically a movs pc,lr in the kernels ret_fast_syscall returning to some thumb mode user space code but store_reg unconditionally aligned the return PC instead of treating the return as an "interworking" branch. I suspect we need to audit all calls to store_reg that might involve the PC to ensure "interworking" branches are correctly handled. Also I'm not quite sure how the code worked before 9b6a3e as the store_reg path wouldn't have triggered the store_cpu_field(var, thumb) to set the processor mode back to thumb. Signed-off-by: Alex Bennée --- target-arm/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.3 diff --git a/target-arm/translate.c b/target-arm/translate.c index 5e21b52..373d68a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4318,7 +4318,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) static void gen_exception_return(DisasContext *s, TCGv_i32 pc) { TCGv_i32 tmp; - store_reg(s, 15, pc); + store_reg_bx(s, 15, pc); tmp = load_cpu_field(spsr); gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp);